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公开(公告)号:US06615341B2
公开(公告)日:2003-09-02
申请号:US09876189
申请日:2001-06-05
申请人: Gilbert C. Sih , Qiuzhen Zou , Inyup Kang , Quaeed Motiwala , Deepu John , Li Zhang , Haitao Zhang , Way-Shing Lee , Charles E. Sakamaki , Prashant A. Kantak , Sanjay K. Jha , Jian Lin
发明人: Gilbert C. Sih , Qiuzhen Zou , Inyup Kang , Quaeed Motiwala , Deepu John , Li Zhang , Haitao Zhang , Way-Shing Lee , Charles E. Sakamaki , Prashant A. Kantak , Sanjay K. Jha , Jian Lin
IPC分类号: G06F9302
CPC分类号: G06F9/3816 , G06F9/30014 , G06F9/30098 , G06F9/30149 , G06F9/30152 , G06F9/3885 , G06F15/7857
摘要: A digital signal processor (DSP) employs a variable-length instruction set. A portion of the variable-length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. The instructions may contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. The DSP includes multiple data buses, and in particular three data buses. The DSP may also use a register bank that has registers accessible by at least two processing units, allowing multiple operations to be performed on a particular set of data by the multiple processing units, without reading and writing the data to and from a memory. an instruction fetch unit that receives instructions of variable length stored in an instruction memory. An instruction memory may advantageously be separate from the three data memories. An instruction decoder decodes the instructions from the instruction memory and generates control signals that cause data to be exchanged between the various registers, data memories, and functional units, allowing multiple operations to be performed during each clock cycle.
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公开(公告)号:US06425070B1
公开(公告)日:2002-07-23
申请号:US09044086
申请日:1998-03-18
申请人: Qiuzhen Zou , Gilbert C. Sih , Inyup Kang , Quaeed Motiwala , Deepu John , Li Zhang , Haitao Zhang , Way-Shing Lee
发明人: Qiuzhen Zou , Gilbert C. Sih , Inyup Kang , Quaeed Motiwala , Deepu John , Li Zhang , Haitao Zhang , Way-Shing Lee
IPC分类号: G06F9302
CPC分类号: G06F9/3816 , G06F9/30014 , G06F9/30098 , G06F9/30149 , G06F9/30152 , G06F9/3885 , G06F15/7857
摘要: The present invention is a novel and improved method and circuit for digital signal processing. One aspect of the invention calls for the use of a variable length instruction set. A portion of the variable length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. Furthermore, additional aspects of the invention are realized by having instructions contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. Thus, multiple operations are performed during each clock cycle, reducing the total number of clock cycles necessary to perform a task. The exemplary DSP includes a set of three data buses over which data may be exchanged with a register bank and three data memories. The use of more than two data buses, and especially three data buses, realizes another aspect of the invention, which is significantly reduced bus contention. One embodiment of the invention calls for the data buses to include one wide bus and two narrow buses. The wide bus is coupled to a wide data memory and the two narrow buses are coupled to two narrow data memories. Another aspect of the invention is realized by the use of a register bank that has registers accessible by at least two processing units. This allows multiple operations to be performed on a particular set of data by the multiple processing units, without reading and writing the data to and from a memory. The processing units in the exemplary embodiment of the invention include an arithmetic logic (ALU) and a multiply-accumulate (MAC) unit. When combined with the use of the multiple bus architecture, highly parallel instructions, or both, an additional aspect of the invention is realized where highly pipelined, multi-operation, processing is performed.
摘要翻译: 本发明是用于数字信号处理的新颖且改进的方法和电路。 本发明的一个方面要求使用可变长度指令集。 可变长度指令的一部分可以存储在存储器空间内的相邻位置,同时跨越存储器字边界的指令的开始和结束。 此外,通过使指令包含可变数量的指令片段来实现本发明的附加方面。 每个指令片段导致执行特定操作或操作,允许在每个时钟周期期间进行多个操作。 因此,在每个时钟周期期间执行多个操作,减少执行任务所需的总时钟周期数。 示例性DSP包括一组三个数据总线,数据可以通过该数据总线与寄存器组和三个数据存储器交换。 使用两条以上的数据总线,特别是三条数据总线,实现了本发明的另一方面,这显着减少了总线竞争。 本发明的一个实施例要求数据总线包括一个宽的总线和两个窄的总线。 宽总线耦合到宽数据存储器,并且两个窄总线耦合到两个窄数据存储器。 通过使用具有可由至少两个处理单元访问的寄存器的寄存器组来实现本发明的另一方面。 这允许通过多个处理单元对特定数据集执行多个操作,而不向存储器读取和写入数据。 本发明的示例性实施例中的处理单元包括算术逻辑(ALU)和乘法累加(MAC)单元。 当结合使用多总线架构,高度并行指令或两者时,实现本发明的另一方面,其中执行高度流水线化,多操作的处理。
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公开(公告)号:US12043952B2
公开(公告)日:2024-07-23
申请号:US18102894
申请日:2023-01-30
申请人: Li Zhang
发明人: Li Zhang
CPC分类号: D06F75/16 , D06F75/20 , D06F75/24 , D06F75/265
摘要: The present disclosure provides an electric steam iron, comprising: a housing provided with a water injection unit, the water injection unit being configured to injecting water; a heating unit comprising a heating shell and a heating element, a first chamber and a second chamber being set in the heating shell, the first chamber is configured for receiving water from the water injection unit; the heating shell is in the first chamber and heats the water in the first chamber to generate steam; the second chamber is connected with the first chamber to receive steam in the first chamber; a first lead-out hole is defined in a bottom of the first chamber; a cover is provided to cover a bottom of the heating shell a steam ironing plate, a steam channel is on the steam ironing plate, the steam channel being distributed on the steam ironing plate in a roundabout manner.
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公开(公告)号:USD1011451S1
公开(公告)日:2024-01-16
申请号:US29897344
申请日:2023-07-13
申请人: Li Zhang
设计人: Li Zhang
摘要: FIG. 1 is a front, right and top perspective view of a balance beam, showing my design.
FIG. 2 is a rear, left and bottom perspective view thereof.
FIG. 3 is a front elevation view thereof.
FIG. 4 is a rear elevation view thereof.
FIG. 5 is an enlarged left side elevation view thereof.
FIG. 6 is an enlarged right side elevation view thereof.
FIG. 7 is a top plan view thereof.
FIG. 8 is a bottom plan view thereof.
FIG. 9 is an enlarged view of detail 9 in FIG. 1; and,
FIG. 10 is an enlarged view of detail 10 in FIG. 2.
The broken lines depict portions of the balance beam that form no part of the claimed design. The dot-dash broken lines in FIGS. 1, 2, 9, and 10 depict the boundaries of the enlargements that form no part of the claimed design.-
公开(公告)号:USD1007331S1
公开(公告)日:2023-12-12
申请号:US29881142
申请日:2022-12-28
申请人: Li Zhang
设计人: Li Zhang
摘要: FIG. 1 is a bottom perspective view of stackable storage unit, showing my new design;
FIG. 2 is a front view thereof;
FIG. 3 is a rear view thereof;
FIG. 4 is a left side view thereof;
FIG. 5 is a right side view thereof;
FIG. 6 is a top view thereof; and,
FIG. 7 is a bottom view thereof.
The broken lines in the drawings illustrate the portions of the stackable storage unit, which form no part of the claimed design.-
公开(公告)号:US20200228269A1
公开(公告)日:2020-07-16
申请号:US16650577
申请日:2018-05-10
摘要: Embodiments of the present disclosure provide methods, devices and a computer readable medium for a restriction on a measurement for a neighbor cell. According to a method implemented by a network device in a communication system, the network device determines a neighbor cell on a frequency layer capable of cell reference signal (CRS) muting. A cell reference signal in the neighbor cell is transmitted on a predetermined physical resource if the neighbor cell enables CRS muting. In response to the determination, the network device transmits measurement restriction information to a terminal device in a cell of the network device. The measurement restriction information indicates that a radio resource management (RRM) measurement for any neighbor cell on the frequency layer is restricted to be performed on the predetermined physical resource. The embodiments of the present disclosure improve a measurement for a neighbor cell.
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公开(公告)号:US10577506B2
公开(公告)日:2020-03-03
申请号:US16019549
申请日:2018-06-27
申请人: Li Zhang
发明人: Li Zhang
摘要: Provided are a BZ glaze enamel painting material composition and a painting method. The composition is a painting material composition composed of natural mineral pigment powder, synthetic resin, and vinyl acetate-acrylate added with a color glaze, a white toning glaze, and a colorless toning glaze at different percentages. The painting method that uses the composition includes the steps of preparing painting canvas, forming bottom, and making picture. In the step of making picture, a suitable amount of BZ glaze enamel painting material composition is prepared according to the size of the painting canvas and, and after being sufficiently stirred, added with temperature-resistant minerals and water according to predetermined weight ratios to respectively form red glaze, yellow glaze, blue glaze, green glaze, purple glaze, orange glaze, and cyan glaze, followed by mixing to product a BZ painting artwork exhibiting, in the entirety thereof, an irregular pattern.
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公开(公告)号:US10051633B2
公开(公告)日:2018-08-14
申请号:US14419301
申请日:2012-08-03
申请人: Li Zhang , Hai Peng Lei , Chun Hai Yao
发明人: Li Zhang , Hai Peng Lei , Chun Hai Yao
摘要: A method including: using first information and second information to determine a code book size, said first information including information for at least one first subframe of at least one cell for which feedback information is to be provided, said at least one first subframe is prior to subframe n and second information for at least one second subframe of at least one cell for which feedback information is to be provided, said at least one second subframe being after said subframe n; and using said code book size for providing feedback information.
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公开(公告)号:US20180141873A1
公开(公告)日:2018-05-24
申请号:US15559056
申请日:2015-10-28
申请人: Li Zhang
发明人: Li Zhang
CPC分类号: C04B41/86 , B44C1/005 , C04B33/24 , C04B33/34 , C04B41/0072 , C04B41/009 , C04B41/5022 , C04B41/526 , C04B41/89 , C04B2111/82 , C09C1/0009 , C04B41/4539 , C04B2103/54
摘要: A high-temperature color glaze painting pigment includes a color glaze, white toning glaze and colorless toning glaze, wherein the color glaze consists of 50 wt % to 66 wt % high temperature resistant white glaze mineral and 50 wt % to 34 wt % water, the white toning glaze consists of 70 wt % high temperature resistant white glaze mineral and 30 wt % water, and the colorless toning glaze consists of 30 wt % high temperature resistant colorless glaze mineral and 70 wt % water, wherein the weight ratio of the color glaze to the white toning glaze is 12.5:1 to 50:1, the weight ratio of the color glaze to the colorless toning glaze is 20:1 to 100:1. The high temperature colored glaze painting pigment and a method for making a porcelain plate painting thereof can be not only manually completed by artists with their experiences, but completed by an industrial production way.
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公开(公告)号:US09900619B2
公开(公告)日:2018-02-20
申请号:US14409785
申请日:2012-07-09
申请人: Ying Chen , Xin Zhao , Li Zhang , Marta Karczewicz
发明人: Ying Chen , Xin Zhao , Li Zhang , Marta Karczewicz
IPC分类号: H04N19/597 , H04N19/105 , H04N19/159 , H04N19/196 , H04N19/176 , H04N19/107
CPC分类号: H04N19/597 , H04N19/105 , H04N19/107 , H04N19/159 , H04N19/176
摘要: In one example, a device for coding video data includes a video coder configured to determine, for a depth block of a depth component of video data, a co-located texture block of a corresponding texture component, and when at least a portion of the texture block corresponds to a prediction unit of the texture component that is not intra-prediction coded: disable an inter-component Wedgelet depth modeling mode for the depth block, select an intra-prediction coding mode for the depth block other than the disabled inter-component Wedgelet depth modeling mode, and code the depth block using the selected intra-prediction coding mode.
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