公开(公告)号：US06246161B1

公开(公告)日：2001-06-12

申请号：US09159061

申请日：1998-09-23

Applicant: Takao Kawamura ,  Hisashi Nose ,  Eisuke Inoue

Inventor： Takao Kawamura ,  Hisashi Nose ,  Eisuke Inoue

IPC: H01J548

CPC classification number: H01J9/263 ,  H01J29/925

Abstract: A cathode ray tube has a vacuum envelope formed of a panel portion supporting a phosphor film on an inner surface thereof, a neck housing an electron gun, a funnel joining the panel and the neck, and a stem sealing an open end of the neck and mounting the electron gun via a plurality of pins extending through the stem. The inside diameters at the open end sealed by the stem and vicinities thereof become gradually larger toward the open end sealed by the stem, or retain at least a value substantially equal to an inside diameter of a major portion of the neck.

Abstract translation: 阴极射线管具有由其内表面上支撑荧光膜的面板部分，容纳电子枪的颈部，连接面板和颈部的漏斗以及密封颈部的开口端的杆形成的真空外壳，以及 通过延伸穿过杆的多个销安装电子枪。 由杆部及其附近密封的开口端的内径朝向由杆密封的开口端逐渐变大，或者保持至少大致等于颈部的主要部分的内径的值。

公开(公告)号：US06271691B1

公开(公告)日：2001-08-07

申请号：US09605887

申请日：2000-06-29

Applicant: Kenji Toyoda ,  Kimio Maruyama ,  Eisuke Inoue

Inventor： Kenji Toyoda ,  Kimio Maruyama ,  Eisuke Inoue

IPC: H03K522

CPC classification number: H03F3/393 ,  H03K5/249

Abstract: A chopper type voltage comparison circuit is disclosed which restrain leakage current between an input and output nodes of each amplifying circuit to enable normal voltage comparisons even if a threshold voltage for each transistor is reduced to diminish a power supply voltage. This chopper type voltage comparison circuit comprises a capacitor C1 having an input voltage or a reference voltage selectively supplied to one end thereof depending on whether a voltage input operation or a voltage comparison operation is to be performed, a CMOS clocked inverter circuit CINV1 for voltage amplification having a voltage at the other end of the capacitor input to an input node thereof and having a clock gate section biased so as to be constantly conductive, and a CMOS clocked inverter circuit CINV4 for input voltage setting having the same circuit configuration as the CMOS clocked inverter circuit for voltage amplification, having an input and output nodes short-circuited thereto, and connected to the input node of the CMOS clocked inverter circuit for voltage amplification so that the clock gate section is switch-controlled to be turned on for the voltage input operation, while the clock gate section is switch-controlled to be turned off for the voltage comparison operation.

Abstract translation: 公开了一种斩波型电压比较电路，其抑制每个放大电路的输入和输出节点之间的漏电流，以便即使降低每个晶体管的阈值电压以减小电源电压，也能进行正常电压比较。 该斩波型电压比较电路包括：电容器C1，其具有根据是否要执行电压输入操作或电压比较操作选择性地提供给其一端的输入电压或参考电压;用于电压放大的CMOS时钟反相器电路CINV1 在输入到其输入节点的电容器的另一端处具有电压，并且具有偏置以恒定导通的时钟门极部分;以及具有与CMOS时钟相同的电路配置的输入电压设置的CMOS时钟反相器电路CINV4 用于电压放大的逆变器电路，具有与其短路的输入和输出节点，并连接到CMOS时钟反相器电路的输入节点用于电压放大，使得时钟门极部分被开关控制为导通，用于电压输入 操作时，而对于电压比较运算，时钟门极段被开关控制为截止 ation。

公开(公告)号：US5233265A

公开(公告)日：1993-08-03

申请号：US561678

申请日：1990-08-01

Applicant: Yukio Takasaki ,  Kazutaka Tsuji ,  Tatsuo Makishima ,  Tadaaki Hirai ,  Sachio Ishioka ,  Tatsuro Kawamura ,  Keiichi Shidara ,  Eikyu Hiruma ,  Kenkichi Tanioka ,  Junichi Yamazaki ,  Kenji Sameshima ,  Hirokazu Matsubara ,  Kazuhisa Taketoshi ,  Mitsuo Kosugi ,  Shiro Suzuki ,  Takashi Yamashita ,  Masaaki Aiba ,  Yoshizumi Ikeda ,  Tsuyoshi Uda ,  Naohiro Goto ,  Yasuhiko Nonaka ,  Eisuke Inoue ,  Hirofumi Ogawa

Inventor： Yukio Takasaki ,  Kazutaka Tsuji ,  Tatsuo Makishima ,  Tadaaki Hirai ,  Sachio Ishioka ,  Tatsuro Kawamura ,  Keiichi Shidara ,  Eikyu Hiruma ,  Kenkichi Tanioka ,  Junichi Yamazaki ,  Kenji Sameshima ,  Hirokazu Matsubara ,  Kazuhisa Taketoshi ,  Mitsuo Kosugi ,  Shiro Suzuki ,  Takashi Yamashita ,  Masaaki Aiba ,  Yoshizumi Ikeda ,  Tsuyoshi Uda ,  Naohiro Goto ,  Yasuhiko Nonaka ,  Eisuke Inoue ,  Hirofumi Ogawa

IPC: H01J29/45 ,  H01L31/0376 ,  H01L31/09 ,  H01L31/107 ,  H01L31/20

CPC classification number: H01J29/456 ,  H01L31/03765 ,  H01L31/095 ,  H01L31/107 ,  H01L31/204 ,  Y02E10/548 ,  Y02P70/521

Abstract: A photoconductive device having a photoconductive layer which includes an amorphous semiconductor layer capable of charge multiplication in at least a part thereof is disclosed. The method of operating such a photoconductive device is also disclosed. By using the avalanche effect of the amorphous semiconductor layer, it is possible to realize a highly sensitive photoconductive device while maintaining low lag property. In one aspect of the present invention, the amorphous semiconductor layer is amorphous Se. In another aspect of the present invention, the amorphous semiconductor layer is composed mainly of tetrahedral elements including at least an element of hydrogen or halogens. When using the amorphous semiconductor layer composed mainly of tetrahedral elements, the charge multiplication effect is produced mainly in the interior of the amorphous semiconductor, and thus it is possible to obtain a thermally stable photoconductive device having a high sensitivity while keeping a good photoresponse.

Abstract translation: 公开了一种具有光电导层的光电导器件，该光电导层包括至少部分能够进行电荷倍增的非​​晶半导体层。 还公开了操作这种光电导器件的方法。 通过使用非晶半导体层的雪崩效应，可以实现高灵敏度的感光器件，同时保持低滞后特性。 在本发明的一个方面，非晶半导体层是非晶态Se。 在本发明的另一方面，非晶半导体层主要由至少包含氢或卤素元素的四面体元素组成。 当使用主要由四面体元素组成的非晶半导体层时，电荷倍增效应主要在非晶半导体的内部产生，因此可以获得具有高灵敏度的热稳定的光电导器件，同时保持良好的光响应。

公开(公告)号：US4866332A

公开(公告)日：1989-09-12

申请号：US16403

申请日：1987-02-19

Applicant: Yukio Takasaki ,  Tatsuo Makishima ,  Kazutaka Tsuji ,  Tadaaki Hirai ,  Eisuke Inoue ,  Yasuhiko Nonaka ,  Naohiro Goto ,  Masanao Yamamoto ,  Keiichi Shidara ,  Kenkichi Tanioka ,  Takashi Yamashita ,  Tatsuro Kawamura ,  Eikyuu Hiruma ,  Shirou Suzuki ,  Masaaki Aiba

Inventor： Yukio Takasaki ,  Tatsuo Makishima ,  Kazutaka Tsuji ,  Tadaaki Hirai ,  Eisuke Inoue ,  Yasuhiko Nonaka ,  Naohiro Goto ,  Masanao Yamamoto ,  Keiichi Shidara ,  Kenkichi Tanioka ,  Takashi Yamashita ,  Tatsuro Kawamura ,  Eikyuu Hiruma ,  Shirou Suzuki ,  Masaaki Aiba

IPC: H01J29/45

CPC classification number: H01J29/456

Abstract: A target of an image pickup tube, having a transparent substrate, a transparent conductive film, a p-type photoconductive film made mainly from amorphous Se, and an n-type conductive film capable of forming a rectifying contact at the interface with the p-type photoconductive film, using the rectifying contact as a reverse bias, characterized in that the p-type photoconductive film containing at least a region having more than 35%, and to 60% by weight of Te in the film thickness direction, and at least a region containing 0.005 to 5% by weight of at least a material capable of forming shallow levels in the amorphous Se in the film thickness direction, has good after-image characteristics even if operated at a high temperature.

Abstract translation: 具有透明基板，透明导电膜，主要由非晶形Se形成的p型光电导膜的图像拾取管的目标和能够在与p型交联的界面处形成整流接触的n型导电膜， 使用整流接触作为反向偏压，其特征在于，所述p型光电导膜至少含有在膜厚度方向上具有大于35％的区域和至少60重量％的Te，至少 至少含有0.005〜5重量％的能够在膜厚度方向上形成非晶态Se的浅层的材料的区域即使在高温下操作也具有良好的后图像特性。