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公开(公告)号：US20130145188A1
公开(公告)日：2013-06-06
申请号：US13308884
申请日：2011-12-01
IPC分类号： G06F1/32
CPC分类号： G06F1/3293 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A mechanism for power management of processors using Pstates is provided. In a chiplet of a processor in a data processing system, a request is received to change a Pstate from a current Pstate to a requested Pstate. A determination is made as to whether the requested Pstate is less than or equal to a maximum Pstate. Responsive to the requested Pstate being less than or equal to the maximum Pstate, a frequency associated with the requested Pstate is computed thereby forming a computed frequency. An operating frequency of the chiplet is then adjusted to the computed frequency without involvement from a central power control entity.
摘要翻译： 提供了使用Pstates处理器进行电源管理的机制。 在数据处理系统中的处理器的小灯中，接收到将Pstate从当前Pstate更改为所请求的Pstate的请求。 确定所请求的Pstate是否小于或等于最大Pstate。 响应于所请求的Pstate小于或等于最大Pstate，计算与所请求的Pstate相关联的频率，从而形成计算出的频率。 然后将小灯的工作频率调整到计算出的频率，而不受中央功率控制实体的参与。
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12.发明申请公开(公告)号：US20120054374A1
公开(公告)日：2012-03-01
申请号：US12869535
申请日：2010-08-26
IPC分类号： G06F3/00
CPC分类号： G06F11/3442 , G06F11/3476 , G06F2201/88 , G06F2201/885
摘要： According to one aspect of the present disclosure a method and technique for monitoring memory access is disclosed. The method includes monitoring access to a memory unit, updating an activity cache associated with an incrementor with access data corresponding to accesses to the memory unit, monitoring a rate of access to the memory unit, adjusting a sample rate of the access data for storage in the memory unit based on the rate of access, and scaling a value of the access data based on the sample rate.
摘要翻译： 根据本公开的一个方面，公开了一种用于监视存储器访问的方法和技术。 该方法包括监视对存储器单元的访问，使用与对存储器单元的访问相对应的访问数据来更新与增量器相关联的活动高速缓存，监视对存储器单元的访问速率，调整访问数据的采样率以便存储 基于访问速率的存储器单元，以及基于采样率来缩放访问数据的值。
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13.发明授权Apparatus and method for simultaneously presenting error interrupt and error data to a support processor 失效同时向支持处理器提供错误中断和错误数据的装置和方法
公开(公告)号：US5267246A
公开(公告)日：1993-11-30
申请号：US213560
申请日：1988-06-30
CPC分类号： G06F11/0772 , G06F11/2736
摘要： Apparatus and method for collecting and analyzing machine check interrupts generated by a central processor complex. Each logic card is scanned to detect the presence of error data generated by logic circuits on the card. A primary maintenance interface card collects the interrupt information identifying the interrupt as to type of interrupt and location of the card generating the interrupt. A system support adapter reports the collected interrupt information over a LAN to a support processor which may thereafter initiate diagnostic operations with the central processor complex.
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公开(公告)号：US5008885A
公开(公告)日：1991-04-16
申请号：US291544
申请日：1988-12-29
IPC分类号： G06F11/22 , G06F11/00 , G06F11/26 , G06F11/267
CPC分类号： G06F11/2215 , G06F11/076 , G06F11/261
摘要： Programmable masks at ascending levels of processing machine functionality support the programmed injection of errors in response to machine events and machine states and in synchronism with machine operation. Provision is made for varying characteristics of injected errors through a programmable error mask and through generation of an injected error wave form having variable temporal and duration characteristics.
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15.发明授权Apparatus for partitioned clock stopping in response to classified processor errors 失效用于响应于分类的处理器错误而分隔时钟停止的装置
公开(公告)号：US4916697A
公开(公告)日：1990-04-10
申请号：US211469
申请日：1988-06-24
申请人： Thomas J. Roche , Gregory S. Still
发明人： Thomas J. Roche , Gregory S. Still
CPC分类号： G06F11/0724 , G06F1/10 , G06F11/0793
摘要： This apparatus stops the clock for a processor partition consisting of a group of processor units in response to detection and classification of an error in a processor unit which can cause a cascade of errors in the partition group.
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