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公开(公告)号：US07757137B2
公开(公告)日：2010-07-13
申请号：US11691856
申请日：2007-03-27
IPC分类号： G01R31/28
CPC分类号： G01R31/318541 , G01R31/318575
摘要： The invention includes a novel scan chain structure for LSSD or GSD IC operation. The scan chain structure includes a first flip-flop (L1) and a second flip-flop (L2) configured to operate the first flip-flop (L1) in normal mode operation, in scan mode operation, in initialization mode and in low leakage power mode operation, wherein each flip-flop within a long scan chain of latches includes a data input, data output, a clock input, a scan-in input and a scan-out output, arranged for normal mode operation. A buffer circuit is electrically connected between the scan-out output of the second flip-flop (L2) and the scan-in input of the first flip-flop (L1) for the next latch in the scan chain, the buffer circuit including a control element that controls the operation the first flip-flop (L1) to scan mode or low power leakage mode. The first flip-flop (L1) is set to a data output value upon exit from low power leakage mode that is the same value that it is set to at initialization during normal mode operation. The switching occurs in only one clock cycle.
摘要翻译： 本发明包括用于LSSD或GSD IC操作的新型扫描链结构。 扫描链结构包括在扫描模式操作中，在初始化模式和低泄漏状态下，被配置为在正常模式操作中操作第一触发器（L1）的第一触发器（L1）和第二触发器（L2） 功率模式操作，其中锁存器的长扫描链内的每个触发器包括布置用于正常模式操作的数据输入，数据输出，时钟输入，扫描输入和扫描输出输出。 缓冲电路电连接在第二触发器（L2）的扫出输出端和第一触发器（L1）的扫描输入端之间用于扫描链中的下一个锁存器，缓冲电路包括一个 控制元件，其控制第一触发器（L1）的扫描模式或低功率泄漏模式的操作。 在从低功率泄漏模式退出时，第一触发器（L1）被设置为数据输出值，该值是在正常模式操作期间初始化时被设置为相同的值。 开关仅在一个时钟周期内发生。
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2.发明申请Signal Delay Element, Method and Integrated Circuit Device for Frequency Adjustment of Electronic Signals 有权用于电子信号频率调整的信号延迟元件，方法和集成电路装置公开(公告)号：US20090021288A1
公开(公告)日：2009-01-22
申请号：US12045894
申请日：2008-03-11
申请人： Florian Braun , Cedric Lichtenau , Thomas Pflueger , Ulrich Weiss
发明人： Florian Braun , Cedric Lichtenau , Thomas Pflueger , Ulrich Weiss
IPC分类号： H03B19/00
CPC分类号： H03K5/156 , H03K5/135 , H03K2005/00052 , H03L7/07 , H03L7/0814
摘要： The invention relates to frequency adjustment of electronic signals. The method comprises the steps of providing an output signal of a frequency generator with a first frequency as input signal for a signal delay element providing an edge of said input signal of said signal delay element; delaying said input signal by adding a delay to each cycle of said input signal until the delayed output signal of the signal delay element is aligned to an edge of said input signal.
摘要翻译： 本发明涉及电子信号的频率调整。 该方法包括以下步骤：提供具有第一频率的频率发生器的输出信号作为提供所述信号延迟元件的所述输入信号的边沿的信号延迟元件的输入信号; 通过向所述输入信号的每个周期添加延迟来延迟所述输入信号，直到信号延迟元件的延迟的输出信号与所述输入信号的边沿对准。
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公开(公告)号：US07106110B2
公开(公告)日：2006-09-12
申请号：US10710681
申请日：2004-07-28
申请人： Miles G. Canada , Erwin B. Cohen , Jay G. Heaslip , Cedric Lichtenau , Thomas Pflueger , Mathew I. Ringler
发明人： Miles G. Canada , Erwin B. Cohen , Jay G. Heaslip , Cedric Lichtenau , Thomas Pflueger , Mathew I. Ringler
IPC分类号： H03B19/00
CPC分类号： G06F1/08 , G06F1/324 , Y02D10/126
摘要： A system and method of shifting a clock frequency of an integrated circuit device from a first frequency to a second frequency, including alternating between the first frequency and the second frequency according to a dithering pattern, the alternating occurring for a predetermined number of cycles; and setting the clock frequency to the second frequency after the predetermined number of cycles.
摘要翻译： 一种将集成电路装置的时钟频率从第一频率转换到第二频率的系统和方法，包括根据抖动模式在第一频率和第二频率之间交替，交替发生预定数量的周期; 并且在预定次数的周期之后将时钟频率设置为第二频率。
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公开(公告)号：US20050104637A1
公开(公告)日：2005-05-19
申请号：US10707066
申请日：2003-11-19
申请人： Rolf Hilgendorf , Jens Kuenzer , Cedric Lichtenau , Thomas Pflueger , Mathew Ringler , Gerard Salem , Peter Sandon , Dana Thygesen , Ulrich Weiss
发明人： Rolf Hilgendorf , Jens Kuenzer , Cedric Lichtenau , Thomas Pflueger , Mathew Ringler , Gerard Salem , Peter Sandon , Dana Thygesen , Ulrich Weiss
IPC分类号： H03L7/06
CPC分类号： H03L7/06
摘要： A synchronization system capable of simultaneously resetting frequency divide-by counters (124A, 124B) of multiple processors (A, B) to zero regardless of the divide-by frequency signal (Mclk/n signal (168A, 168B)) and regardless of the magnitude of the clock mesh delays experienced by the Mclk/n signals in the processors. The synchronization system includes a mesh delay circuit (176A, 176B) for each processor that simulates in the undivided signal (Mclk/1 signal (136A, 136B)) the clock mesh delay experienced by the Mclk/n signal in that processor so as to provide an Lclk signal (172A, 172B). A phase detector detects the phase offset between the Mclk/n signal and the Sysclk signal (112) and sends an asynchronous offset signal (194A, 194B) to a counter re-setter (196A, 196B) that resets the divide-by counter to zero based on the offset signal.
摘要翻译： 能够将多个处理器（A，B）的频率分频计数器（124A，124BB）同时复位的同步系统为零，而不管分频频率 信号（Mclk / n信号（168A，168B）），并且与处理器中的Mclk / n信号经历的时钟网格延迟的大小无关。 同步系统包括用于在未分割信号中模拟的每个处理器的网格延迟电路（176A，176BB）（Mclk / 1信号（136 < / SUB>，136 B））由该处理器中的Mclk / n信号经历的时钟网格延迟，以便提供Lclk信号（172 ，172 B ）。 相位检测器检测Mclk / n信号和Sysclk信号之间的相位偏移（112），并将异步偏移信号（194A，192B）发送到计数器 基于偏移信号将再分配计数器复位为零的重新设置器（196A，196BB）。
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5.发明授权Integrated circuit for writing and reading registers distributed across a semiconductor chip 失效用于写入和读取分布在半导体芯片上的寄存器的集成电路公开(公告)号：US07861129B2
公开(公告)日：2010-12-28
申请号：US12109529
申请日：2008-04-25
申请人： Thuyen Le , Cedric Lichtenau , Martin Padeffke , Thomas Pflueger
发明人： Thuyen Le , Cedric Lichtenau , Martin Padeffke , Thomas Pflueger
IPC分类号： G01R31/28
CPC分类号： G01R31/318558 , G01R31/318555
摘要： An integrated circuit on a semiconductor chip with a plurality of registers distributed across the semiconductor chip. The registers are writeable and readable. The integrated circuit comprises a central control block. The integrated circuit comprises a plurality of circuit units. The circuit unit includes a functional portion with a local clock controller and one or more of the registers. The circuit unit includes a satellite portion. The central control block and the satellite portions are serially connected together and form a scan chain, wherein the scan chain is formed as a ring.
摘要翻译： 一种半导体芯片上的集成电路，具有分布在半导体芯片上的多个寄存器。 寄存器是可写和可读的。 集成电路包括中央控制块。 集成电路包括多个电路单元。 电路单元包括具有本地时钟控制器和一个或多个寄存器的功能部分。 电路单元包括卫星部分。 中央控制块和卫星部分串联在一起并形成扫描链，其中扫描链形成为环。
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公开(公告)号：US20090055637A1
公开(公告)日：2009-02-26
申请号：US11844449
申请日：2007-08-24
IPC分类号： G06F15/177
CPC分类号： G06F21/575 , G06F21/71
摘要： A secure Power-on Reset (POR) engine is provided, inside a processor chip, which guarantees a secure initialization of the chip to enable secure code execution. External access to chip resources is limited to a very few targeted settings that do not compromise the chip security. The POR engine comprises a small state machine that runs through a predefined sequence coded in persistent memory contained in the processor chip. The state machine initializes the chip and allows external access from an external processor to only some scan chains of the processor chip in order to configure interfaces, and the like, without compromising the chip security. The state machine also manages the encryption keys that are used to verify that the code, fetched by the processor to complete the initialization in software, is not modified by a third party.
摘要翻译： 在处理器芯片内提供安全的上电复位（POR）引擎，保证了芯片的安全初始化，从而实现安全的代码执行。 对芯片资源的外部访问仅限于不损害芯片安全性的极少量目标设置。 POR引擎包括一个小型状态机，其运行在包含在处理器芯片中的持久存储器中编码的预定义序列。 状态机初始化芯片，并且允许从外部处理器到处理器芯片的一些扫描链的外部访问，以便配置接口等，而不损害芯片的安全性。 状态机还管理加密密钥，用于验证由处理器获取的以软件完成初始化的代码不被第三方修改。
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7.发明申请Integrated Circuit for Writing and Reading Registers Distributed Across a Semiconductor Chip 失效用于写入和读取寄存器的集成电路分布在半导体芯片中公开(公告)号：US20080270860A1
公开(公告)日：2008-10-30
申请号：US12109529
申请日：2008-04-25
申请人： Thuyen Le , Cedric Lichtenau , Martin Padeffke , Thomas Pflueger
发明人： Thuyen Le , Cedric Lichtenau , Martin Padeffke , Thomas Pflueger
CPC分类号： G01R31/318558 , G01R31/318555
摘要： An integrated circuit on a semiconductor chip with a plurality of registers distributed across the semiconductor chip. The registers are writeable and readable. The integrated circuit comprises a central control block. The integrated circuit comprises a plurality of circuit units. The circuit unit includes a functional portion with a local clock controller and one or more of the registers. The circuit unit includes a satellite portion. The central control block and the satellite portions are serially connected together and form a scan chain, wherein the scan chain is formed as a ring.
摘要翻译： 一种半导体芯片上的集成电路，具有分布在半导体芯片上的多个寄存器。 寄存器是可写和可读的。 集成电路包括中央控制块。 集成电路包括多个电路单元。 电路单元包括具有本地时钟控制器和一个或多个寄存器的功能部分。 电路单元包括卫星部分。 中央控制块和卫星部分串联在一起并形成扫描链，其中扫描链形成为环。
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8.发明申请System, apparatus and method of providing accurate time-based counters for scaling operating frequencies of microprocessors 失效提供精确的基于时间的计数器的系统，装置和方法，用于缩放微处理器的工作频率公开(公告)号：US20070172010A1
公开(公告)日：2007-07-26
申请号：US11340449
申请日：2006-01-26
申请人： Rolf Hilgendorf , Jens Kuenzer , Cedric Lichtenau , Thomas Pflueger , Martin Recktenwald , Andreas Schmid
发明人： Rolf Hilgendorf , Jens Kuenzer , Cedric Lichtenau , Thomas Pflueger , Martin Recktenwald , Andreas Schmid
IPC分类号： H04L7/00
摘要： The illustrative embodiments provide a system, apparatus and method for providing accurate time-based counters for scaling operating frequencies of microprocessors. The system, apparatus and method make use of a time-based counter circuit configuration in which a fixed frequency clock is derived from a PLL of the clock generation circuit of the microprocessor and is used to feed the external and internal timebase logic as well as a timebase accumulator counter. The timebase accumulator counter accumulates the tick events from the timebase logic between two core clocks. The accumulated value is transferred to the core clock domain on every clock edge of a scalable clock and the accumulator is then reset. Because the accumulated ticks are transferred to the core clock domain before the accumulator is reset, no ticks are ever lost using the circuitry of the illustrative embodiment.
摘要翻译： 说明性实施例提供了一种用于提供用于缩放微处理器的操作频率的精确的基于时间的计数器的系统，装置和方法。 系统，装置和方法利用基于时间的计数器电路配置，其中固定频率时钟源自微处理器的时钟产生电路的PLL，并用于馈送外部和内部时基逻辑以及 时基累加器计数器。 时基累加器计数器从两个核心时钟之间的时基逻辑累加tick事件。 累加值在可伸缩时钟的每个时钟沿传输到核心时钟域，然后累加器复位。 因为在累加器复位之前累积的刻度被传送到核心时钟域，所以使用说明性实施例的电路不会丢失任何刻度。
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公开(公告)号：US06967510B2
公开(公告)日：2005-11-22
申请号：US10687251
申请日：2003-10-16
CPC分类号： G06F1/14
摘要： The present invention provides for supporting an on chip-timer facility and, more particularly, to the generation of a constant time incremental increase while changing core mesh-clock frequency. A latch is coupled to the output of a first free-running clock. An inverter is coupled to the output of the first latch. At least one other secondary latch is coupled to the output of the first latch. An edge detector is coupled to the output of the secondary latch. An incrementer or decrementer is coupled to the output of the edge detector. A memory is coupled to the output of the incrementer or decrementer.
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10.发明授权Method for controlling the supply voltage for an integrated circuit and an apparatus with a voltage regulation module and an integrated circuit 失效用于控制集成电路的电源电压的方法和具有电压调节模块和集成电路的装置公开(公告)号：US08471624B2
公开(公告)日：2013-06-25
申请号：US13037343
申请日：2011-02-28
IPC分类号： G05F3/02
CPC分类号： G05F1/56
摘要： The present invention relates to a method for controlling the supply voltage for an integrated circuit, which is connected to a voltage regulation module via a sense line, a voltage supply line and a bus wherein the supply voltage is provided by the voltage regulation module (10) via the voltage supply line. The supply voltage is composed of a reference voltage and a number of additional voltage levels. The reference voltage is defined by a voltage source and controlled by the integrated circuit via the bus, and the number of additional voltage levels is determined by the integrated circuit and send to the voltage regulation module via the sense line. Further the present invention relates to a corresponding apparatus with a voltage regulation module and an integrated circuit.
摘要翻译： 本发明涉及一种用于控制集成电路的电源电压的方法，该集成电路通过感测线，电压供应线和总线连接到电压调节模块，其中电源电压由电压调节模块（10 ）通过电源线。 电源电压由参考电压和多个附加电压电平组成。 参考电压由电压源定义，并通过总线由集成电路控制，附加电压电平的数量由集成电路确定，并通过感测线发送到电压调节模块。 此外，本发明涉及具有电压调节模块和集成电路的相应装置。
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