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公开(公告)号：US07583402B2
公开(公告)日：2009-09-01
申请号：US11258879
申请日：2005-10-27
CPC分类号： G06K15/00 , G03G15/50 , G03G21/04 , H04N1/32358 , H04N1/4446 , H04N2201/0091 , H04N2201/3288 , H04N2201/3295
摘要： This image forming device 1 comprises an image processing unit 9, an HDD 23 and an image forming unit. The image processing unit 9 is capable of instructing the output of the image data sent from the PC 43. The HDD 23 is connected to the image processing unit 9 and is capable of storing the image data to be delivered. The image forming unit is capable of receiving the instruction from the image processing unit 9 and delivering onto paper or the like the image data stored in the HDD 23. Then, when the ID information contained in the image data is detected by the image processing unit 9, writing of image data to the HDD 23 is prohibited.
摘要翻译： 该图像形成装置1包括图像处理单元9，HDD 23和图像形成单元。 图像处理单元9能够指示从PC 43发送的图像数据的输出。HDD 23连接到图像处理单元9，并且能够存储要传送的图像数据。 图像形成单元能够接收来自图像处理单元9的指令并将存储在HDD 23中的图像数据传送到纸张上。然后，当图像处理单元检测到包含在图像数据中的ID信息时， 9，禁止向HDD23写入图像数据。
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公开(公告)号：US07548337B2
公开(公告)日：2009-06-16
申请号：US11258881
申请日：2005-10-27
CPC分类号： G06K15/00 , H04N1/00347 , H04N1/32358 , H04N2201/001 , H04N2201/0015 , H04N2201/0087 , H04N2201/0091 , H04N2201/3288 , H04N2201/3295
摘要： This image forming device 1 comprises a control unit, a connector interface 31, an external memory 33, and an image forming unit. The control unit instructs the output of a predetermined image data. The connector interface 31 is connected to the control unit. The external memory 14 can be removably connected to the connector interface 31 while it stores the output image data. The image forming unit is capable of receiving the instruction from the control unit and delivering onto paper the image data stored in the external memory 14.
摘要翻译： 该图像形成装置1包括控制单元，连接器接口31，外部存储器33和图像形成单元。 控制单元指示预定图像数据的输出。 连接器接口31连接到控制单元。 外部存储器14可以可拆卸地连接到连接器接口31，同时存储输出图像数据。 图像形成单元能够接收来自控制单元的指令并将存储在外部存储器14中的图像数据传送到纸上。
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公开(公告)号：US20070097433A1
公开(公告)日：2007-05-03
申请号：US11258881
申请日：2005-10-27
IPC分类号： G06K15/00
CPC分类号： G06K15/00 , H04N1/00347 , H04N1/32358 , H04N2201/001 , H04N2201/0015 , H04N2201/0087 , H04N2201/0091 , H04N2201/3288 , H04N2201/3295
摘要： This image forming device 1 comprises a control unit, a connector interface 31, an external memory 33, and an image forming unit. The control unit instructs the output of a predetermined image data. The connector interface 31 is connected to the control unit. The external memory 14 can be removably connected to the connector interface 31 while it stores the output image data. The image forming unit is capable of receiving the instruction from the control unit and delivering onto paper the image data stored in the external memory 14.
摘要翻译： 该图像形成装置1包括控制单元，连接器接口31，外部存储器33和图像形成单元。 控制单元指示预定图像数据的输出。 连接器接口31连接到控制单元。 外部存储器14可以可拆卸地连接到连接器接口31，同时存储输出图像数据。 图像形成单元能够接收来自控制单元的指令并将存储在外部存储器14中的图像数据传送到纸上。
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公开(公告)号：US5878162A
公开(公告)日：1999-03-02
申请号：US345819
申请日：1994-11-21
CPC分类号： H04N1/00867 , H04N1/0087 , H04N2201/3205 , H04N2201/327 , H04N2201/3271
摘要： An image processing circuit which adds, by means of a yellow color image data, forgery tracing information to yellow, magenta and cyan color image data obtained by reading out of an original. A tracing information adder replaces the read-out yellow color image data with a yellow color image of a higher density in a low-density area where the density of the read-out yellow color image data is equal to or below a set threshold value. In a high-density area where the density of the read-out yellow color image data exceeds the set threshold value, the tracing information is added by adding a predetermined value to the read-out yellow color image data.
摘要翻译： 一种图像处理电路，其通过黄色图像数据添加伪造跟踪信息到通过读出原件获得的黄色，品红色和青色图像数据。 跟踪信息加法器在读出的黄色图像数据的浓度等于或低于设定阈值的低密度区域中用黄色更高密度的黄色图像代替所读出的黄色图像数据。 在读出的黄色图像数据的浓度超过设定的阈值的高密度区域中，通过向读出的黄色图像数据添加预定值来追加跟踪信息。
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公开(公告)号：US5729627A
公开(公告)日：1998-03-17
申请号：US556839
申请日：1995-11-02
CPC分类号： H04N1/40062
摘要： An apparatus for and a method of judging a dotted image area using a small-capacity memory. Image data corresponding to one line out of image data representing an original image are stored in a line memory. On the line corresponding to the image data stored in the line memory, a target pixel is successively set along the main scanning direction. Image data corresponding to the target pixel is compared with image data corresponding to pixels around the target pixel. It is judged whether or not the target pixel is a peculiar point pixel on the basis of the result of the comparison. Further, the distance between peculiar point pixels is operated. The operated distance between the peculiar point pixels is referred to a predetermined judgment basis, to judge whether or not a judging area including the finite number of pixels is a dotted image area.
摘要翻译： 一种使用小容量存储器来判断虚线图像区域的装置和方法。 对应于表示原始图像的图像数据中的一行的图像数据被存储在行存储器中。 在对应于存储在行存储器中的图像数据的行上，沿着主扫描方向连续设置目标像素。 对应于目标像素的图像数据与对应于目标像素周围的像素的图像数据进行比较。 基于比较结果判断目标像素是否是特殊点像素。 此外，操作特殊点像素之间的距离。 特定点像素之间的操作距离参照预定判断基准，判断包括有限像素数的判断区域是否为虚线图像区域。
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公开(公告)号：US5519500A
公开(公告)日：1996-05-21
申请号：US61882
申请日：1993-05-14
申请人： Hidechika Kumamoto
发明人： Hidechika Kumamoto
IPC分类号： B41J2/44 , B41J2/45 , B41J2/455 , G03G21/00 , H03L7/00 , H04N1/036 , H04N1/053 , H04N5/06 , H04N1/23 , B41J2/47
CPC分类号： H04N1/053 , H04N2201/04786
摘要： A synchronization signal generating circuit generates a synchronization signal used to output read data sequentially in a specified period. This circuit is provided with a clock generator means for generating a reference clock, a first counter unit for counting the reference clock; a synchronization signal generator for generating the synchronization signal in a first period in accordance with a count value of the first counter unit; a second counter unit for counting the generation of the synchronization signal; a resetter for resetting the second counter unit when a count value of the second counter unit reaches a specified value; and a period changer for controlling the synchronization signal generator so as to generate the synchronization signal in a second period only when the count value of the second counter unit reaches the specified value. Accordingly, a shift amount of the period of the synchronization signal relative to the specified period in which data are output sequentially does not exceeds a predetermined level.
摘要翻译： 同步信号发生电路产生用于在规定时间内依次输出读取数据的同步信号。 该电路设置有用于产生参考时钟的时钟发生器装置，用于对参考时钟进行计数的第一计数器单元; 同步信号发生器，用于根据第一计数器单元的计数值在第一周期中产生同步信号; 第二计数器单元，用于对同步信号的产生进行计数; 复位器，用于当第二计数器单元的计数值达到指定值时复位第二计数器单元; 以及周期改变器，用于控制同步信号发生器，以便仅在第二计数器单元的计数值达到指定值时在第二周期中产生同步信号。 因此，同步信号相对于其中依次输出数据的指定周期的周期的偏移量不超过预定水平。
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17.发明授权
公开(公告)号：US5418896A
公开(公告)日：1995-05-23
申请号：US669628
申请日：1991-03-14
CPC分类号： G06T3/608 , H04N1/3878
摘要： A skew processing circuit 33 includes two line buffers, a skew processing type line buffer 331 and an original type line buffer 332, and a write/read control circuit 333 for controlling the two line buffers. The write/read control circuit 333 is a control circuit for writing a given image data in the line buffers 331, 332 in single lines and selectively reading the data written in the two line buffers 331, 332. When an image data is written in the original type line buffer 332, addressed are sequentially written from the head address 0. On the other hand, when the image data is written in the skew processing type line buffer 331, a write start address RH0 is determined in correspondence with a skew angle, and the write start address RH0 is shifted in each line to discard the head portion of the image data by specified dots (specified addresses). Thus, by controlling the writing of data in the two line buffers 331, 332 and reading data from them, an image in an arbitrary area can be processed into the skew with an arbitrary angle.
摘要翻译： 歪斜处理电路33包括两条行缓冲器，歪斜处理型行缓冲器331和原始行行缓冲器332，以及用于控制两行缓冲器的写/读控制电路333。 写入/读取控制电路333是用于将线路缓冲器331,332中的给定图像数据以单行写入并选择性地读取写入两行缓冲器331,332中的数据的控制电路。当将图像数据写入 原始类型行缓冲器332，从头地址0顺序写入。另一方面，当图像数据被写入偏斜处理类型行缓冲器331时，写入开始地址RH0与斜角对应地确定， 并且写入开始地址RH0在每行中移位，以通过指定的点（指定的地址）丢弃图像数据的头部。 因此，通过控制两行缓冲器331,332中的数据的写入和从它们读取数据，任意区域中的图像可以被处理成任意角度的偏斜。
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公开(公告)号：US5272546A
公开(公告)日：1993-12-21
申请号：US664313
申请日：1991-03-04
IPC分类号： G02B26/10 , B41J2/44 , B41J2/47 , G06K15/12 , H03K5/00 , H03K5/13 , H03K7/08 , H04N1/036 , H04N1/405 , H04N1/40 , G01D15/00
CPC分类号： H03K5/131 , G06K15/1209 , H03K7/08 , H04N1/4056 , H03K2005/00234
摘要： A laser beam controller comprises a basic pulse signal generating circuit, a delay circuit, a delay control circuit, a pulse generating circuit and a laser beam generator. The basic pulse signal generating circuit generates periodically occurring basic pulse signal. The delay circuit delays the basic pulse signal. The delay control circuit controls the delay time of the basic pulse in the delay circuit according to image data. The pulse generating circuit generates an output pulse having a width corresponding to the delay time of the basic pulse signal. The laser beam generator generates a laser beam for a duration corresponding to the width of the output pulse by said pulse generating circuit. According to the controller, any desired gradation of a pixel of the image is desirably produced.
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公开(公告)号：US5083217A
公开(公告)日：1992-01-21
申请号：US540213
申请日：1990-06-19
申请人： Hidechika Kumamoto
发明人： Hidechika Kumamoto
IPC分类号： G06T11/00
CPC分类号： G06T11/001
摘要： A shadow-added image formation device includes a photoelectric converting mechanism for converting every pixel into an electric signal, A/D-converting mechanism for A/D-converting an output of the photoelectric converting mechanism, a signal converting mechanism for converting an output of the A/D-converting mechanism into a binary serial signal representing white and black pixels, and a detecting mechanism for detecting an area to which shadow can be added from the output of the signal converting mechanism. A shadow signal formation mechanism for outputting a signal, a setting mechanism for setting a shadow area, an adding mechanism for comparing the widths of the areas detected by the detecting mechanism and set by the setting mechanism and adding the shadow signal to the binary serial signal corresponding to the smaller one of the areas determined by the comparison, and a reproducing mechanism for reproducing an image to which the shadow signal has been added, are also provided.
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公开(公告)号：US5072310A
公开(公告)日：1991-12-10
申请号：US523344
申请日：1990-05-14
CPC分类号： G03G15/5066 , H04N1/00962 , H04N1/2104 , H04N1/2158 , H04N1/32561 , G03G2215/00092 , H04N1/00204 , H04N2201/0081 , H04N2201/0082
摘要： An integrated circuit (IC) card for use in an image processing machine, such as a digital copying machine. The IC card includes a first storage area for storing data for controlling said image processor and a second storage area for storing image data to be processed by said image processor.
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