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    Pipeline FFT architecture for a programmable device
    11.
    发明授权
    Pipeline FFT architecture for a programmable device 有权
    可编程器件的管道FFT架构

    公开(公告)号：US08001171B1

    公开(公告)日：2011-08-16

    申请号：US11445066

    申请日：2006-05-31

    Applicant: James M. Simkins ,  Vasisht Mantra Vadi ,  Helen Hai-Jo Tarn

    Inventor： James M. Simkins ,  Vasisht Mantra Vadi ,  Helen Hai-Jo Tarn

    IPC: G06F15/00

    CPC classification number: G06F17/142

    Abstract: A pipeline Fast Fourier Transform (“FFT”) architecture for a programmable device is described. A first Radix-2 butterfly stage is coupled to receive a first input, configured to provide a first output responsive thereto, and configured to truncate at least one Least Significant Bit of the first output. A delay and swap stage is coupled to receive the first output and configured to provide a second output. A second Radix-2 butterfly stage is coupled to receive the second output and a second input, configured to provide a third output responsive thereto, and configured to truncate at least one Most Significant Bit of the third output. The first Radix-2 butterfly stage and the second Radix-2 butterfly stage are implemented in digital signal processing slices of a programmable device.

    Abstract translation: 描述了用于可编程设备的管线快速傅里叶变换（“FFT”）架构。 第一基数2蝴蝶级被耦合以接收第一输入，被配置为响应于此提供第一输出，并且被配置为截断第一输出的至少一个最低有效位。 耦合延迟和交换级以接收第一输出并且被配置为提供第二输出。 第二基数2蝶形级耦合以接收第二输出和第二输入，第二输入被配置为响应于此提供第三输出，并且被配置为截断第三输出的至少一个最高有效位。 第一个Radix-2蝴蝶舞台和第二个Radix-2蝴蝶舞台在可编程设备的数字信号处理片段中实现。

    METHOD OF AND CIRCUIT FOR IMPLEMENTING A FILTER IN AN INTEGRATED CIRCUIT
    13.
    发明申请
    METHOD OF AND CIRCUIT FOR IMPLEMENTING A FILTER IN AN INTEGRATED CIRCUIT 有权
    在一体化电路中实现滤波器的方法和电路

    公开(公告)号：US20100192118A1

    公开(公告)日：2010-07-29

    申请号：US12418979

    申请日：2009-04-06

    Applicant: Xavier Wendling ,  James M. Simkins

    Inventor： Xavier Wendling ,  James M. Simkins

    IPC: G06F17/50

    CPC classification number: G06F7/575 ,  H03H17/06 ,  H03H2017/0692

    Abstract: According to an embodiment of the invention, a method of configuring a filter in a circuit to be implemented in an integrated circuit is disclosed. The method comprises receiving a high level design of the circuit; identifying a filter in the high level design; analyzing coefficients of the filter; and transforming the filter of the high level design to a filter using a processing block of the circuit configured to accommodate a common coefficient, wherein the processing block is coupled to receive taps associated with the common coefficient. A computer program product and a circuit for configuring a filter in a circuit to be implemented in an integrated circuit are also disclosed.

    Abstract translation: 根据本发明的实施例，公开了一种在集成电路中实现的电路中配置滤波器的方法。 该方法包括接收电路的高级设计; 识别高级设计中的过滤器; 分析滤波器的系数; 以及使用被配置为容纳公共系数的所述电路的处理块将所述高级设计的所述滤波器变换为滤波器，其中所述处理块被耦合以接收与所述公共系数相关联的抽头。 还公开了一种用于在集成电路中实现的电路中配置滤波器的计算机程序产品和电路。

    Method and apparatus for locating data transition regions
    15.
    发明授权
    Method and apparatus for locating data transition regions 有权
    用于定位数据过渡区域的方法和装置

    公开(公告)号：US06690201B1

    公开(公告)日：2004-02-10

    申请号：US10058712

    申请日：2002-01-28

    Applicant: James M. Simkins ,  Catalin Baetoniu ,  Nicholas J. Sawyer

    Inventor： James M. Simkins ,  Catalin Baetoniu ,  Nicholas J. Sawyer

    IPC: H03K1900

    CPC classification number: H04L7/02 ,  H03K5/135 ,  H04L7/0012 ,  H04L7/0337

    Abstract: Method and apparatus for data sampling is described. More particularly, a data sampling circuit having a delay line and a plurality of tap circuits is used to sample data and provide a vector indicative of a transition region of a sampled input signal. Additionally, a hybrid sampling circuit is described with a fine grain delay line and coarse grain delay lines. Furthermore, a controller is described for using such a vector to control which data samples are used.

    Abstract translation: 描述用于数据采样的方法和装置。 更具体地，具有延迟线和多个抽头电路的数据采样电路用于采样数据并提供指示采样输入信号的转换区域的矢量。 另外，利用细粒延迟线和粗粒延迟线描述混合采样电路。 此外，描述了使用这样的向量来控制使用哪些数据样本的控制器。

    Digital signal processing block having a wide multiplexer
    16.
    发明授权
    Digital signal processing block having a wide multiplexer 有权
    具有宽多路复用器的数字信号处理块

    公开(公告)号：US07865542B2

    公开(公告)日：2011-01-04

    申请号：US11433120

    申请日：2006-05-12

    Applicant: Bernard J. New ,  Vasisht Mantra Vadi ,  Jennifer Wong ,  Alvin Y. Ching ,  John M. Thendean ,  Anna Wing Wah Wong ,  James M. Simkins

    Inventor： Bernard J. New ,  Vasisht Mantra Vadi ,  Jennifer Wong ,  Alvin Y. Ching ,  John M. Thendean ,  Anna Wing Wah Wong ,  James M. Simkins

    IPC: G06F7/38

    CPC classification number: G06F7/02 ,  G06F7/5443 ,  G06F7/57 ,  G06F7/575 ,  G06F2207/025 ,  G06F2207/3828 ,  G06K9/00986 ,  H03K19/1737

    Abstract: A digital signal processing block having: 1) a first digital signal processing element including: a first multiplexer of a first plurality of multiplexers, the first multiplexer selecting between a first data input and a first zero constant input; and a first arithmetic unit coupled to the first plurality of multiplexers, the first arithmetic logic unit configured for addition; and 2) a second digital signal processing element including: a second multiplexer of a second plurality of multiplexers, the second multiplexer selecting between a second data input and a second zero constant input; and a second arithmetic unit coupled to the second plurality of multiplexers and to a third multiplexer of the first plurality of multiplexers, the second arithmetic unit configured for addition.

    Abstract translation: 一种数字信号处理块，具有：1）第一数字信号处理元件，包括：第一多路复用器的第一多路复用器，所述第一多路复用器在第一数据输入和第一零常数输入之间进行选择; 以及耦合到所述第一多个复用器的第一算术单元，所述第一算术逻辑单元被配置为用于相加; 以及2）第二数字信号处理元件，包括：第二多路复用器的第二多路复用器，所述第二多路复用器在第二数据输入和第二零常数输入之间进行选择; 以及耦合到所述第二多路复用器的第二运算单元和所述第一多路复用器的第三多路复用器，所述第二运算单元被配置为相加。

    DIGITAL SIGNAL PROCESSING BLOCK WITH PREADDER STAGE
    18.
    发明申请
    DIGITAL SIGNAL PROCESSING BLOCK WITH PREADDER STAGE 有权
    数字信号处理块与前级

    公开(公告)号：US20100191786A1

    公开(公告)日：2010-07-29

    申请号：US12360836

    申请日：2009-01-27

    Applicant: James M. Simkins ,  Alvin Y. Ching ,  John M. Thendean ,  Vasisht M. Vadi ,  Chi Fung Poon ,  Muhammad Asim Rab

    Inventor： James M. Simkins ,  Alvin Y. Ching ,  John M. Thendean ,  Vasisht M. Vadi ,  Chi Fung Poon ,  Muhammad Asim Rab

    IPC: G06F5/01 ,  G06F7/50 ,  G06F9/38

    CPC classification number: G06F7/5443 ,  H03H17/06 ,  H03H2220/04 ,  H03H2220/06 ,  H03K19/17732

    Abstract: A digital signal processing block with a preadder stage for an integrated circuit is described. The digital signal processing block includes a preadder stage and a control bus. The control bus is coupled to the preadder stage for dynamically controlling operation of the preadder stage. The preadder stage includes: a first input port of a first multiplexer coupled to the control bus; a second input port of a first logic gate coupled to the control bus; a third input port of a second logic gate coupled to the control bus; and a fourth input port of an adder/subtractor coupled to the control bus.

    Abstract translation: 描述了具有用于集成电路的前级的数字信号处理块。 数字信号处理块包括一个前级和一个控制总线。 控制总线耦合到前级，用于动态地控制前级的操作。 前级级包括：耦合到控制总线的第一多路复用器的第一输入端口; 耦合到控制总线的第一逻辑门的第二输入端口; 耦合到控制总线的第二逻辑门的​​第三输入端口; 以及耦合到控制总线的加法器/减法器的第四输入端口。

    Method and system for maintaining the security of design information
    19.
    发明授权
    Method and system for maintaining the security of design information 有权
    维护设计信息安全的方法和系统

    公开(公告)号：US07757294B1

    公开(公告)日：2010-07-13

    申请号：US10929078

    申请日：2004-08-27

    Applicant: James M. Simkins

    Inventor： James M. Simkins

    IPC: G06F12/14

    CPC classification number: G06F21/10

    Abstract: A method and system for maintaining the security of design information is disclosed. The method includes generating an encrypted IP core by encrypting an IP core using a public key, downloading the encrypted IP core to a programmable logic device (PLD), and recovering the IP core by decrypting the encrypted IP core using a private key. The private key is associated with the PLD, and the public key and the private key correspond to one another. The method may further include the PLD receiving authorization information corresponding to the IP core and comparing local authorization information stored at the PLD with the authorization information.

    Abstract translation: 公开了一种用于维护设计信息的安全性的方法和系统。 该方法包括通过使用公共密钥加密IP核来生成加密的IP核，将加密的IP核下载到可编程逻辑设备（PLD），以及通过使用私钥解密加密的IP核来恢复IP核。 私钥与PLD相关联，公钥和私钥相互对应。 该方法还可以包括PLD接收对应于IP核的授权信息，并将存储在PLD中的本地授权信息与授权信息进行比较。

    Programmable logic device with cascading DSP slices
    20.
    发明授权
    Programmable logic device with cascading DSP slices 有权
    具有级联DSP片的可编程逻辑器件

    公开(公告)号：US07472155B2

    公开(公告)日：2008-12-30

    申请号：US11019783

    申请日：2004-12-21

    Applicant: James M. Simkins ,  Steven P. Young ,  Jennifer Wong ,  Bernard J. New ,  Alvin Y. Ching

    Inventor： James M. Simkins ,  Steven P. Young ,  Jennifer Wong ,  Bernard J. New ,  Alvin Y. Ching

    IPC: G06F7/38

    CPC classification number: H03K19/17736 ,  G06F15/7867 ,  H03K19/17732

    Abstract: Described is a programmable logic device (PLD) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each DSP slice includes a plurality of operand input ports and a slice output port, all of which are programmably connected to general routing and logic resources. The operand ports receive operands for processing, and a slice output port conveys processed results. Each slice additionally includes a feedback port connected to the respective slice output port, to support accumulate functions in this embodiment, and a cascade input port connected to the output port of an upstream slice to support cascading.

    Abstract translation: 描述了可编程逻辑器件（PLD），其具有可以级联的DSP片段，以创建不同大小和复杂度的DSP电路。 每个DSP片包括多个操作数输入端口和片输出端口，所有这些端口都可编程地连接到通用路由和逻辑资源。 操作数端口接收处理的操作数，切片输出端口传送处理结果。 每个切片还包括连接到相应切片输出端口的反馈端口，以支持在该实施例中的累积功能，以及连接到上游切片的输出端口以支持级联的级联输入端口。

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