公开(公告)号：US6159830A

公开(公告)日：2000-12-12

申请号：US363645

申请日：1999-07-30

Applicant: Norbert Galster ,  Pavel Hazdra ,  Jan Vobecky

Inventor： Norbert Galster ,  Pavel Hazdra ,  Jan Vobecky

IPC: H01L29/744 ,  H01L21/265 ,  H01L21/266 ,  H01L21/322 ,  H01L21/426 ,  H01L21/425

CPC classification number: H01L21/26506 ,  H01L21/266

Abstract: In a process for adjusting the carrier lifetime in a semiconductor component (1) by means of particle irradiation (P), at least two defect regions (10, 11, 12, 13) are produced in the semiconductor component (1). In this process, a particle beam (P), consisting of particles (a, b, c, d) with at least approximately the same initial energy, is acted on by at least one means (2), before reaching the semiconductor component (1), in such a way that the particles (a, b, c, d) subsequently have different energy values, at least two energy value groups being distinguishable. It is thereby possible, with a single particle irradiation operation, to produce an arbitrary number of defect regions whose arrangement and weighting is arbitrarily selectable.

Abstract translation: 在通过粒子照射（P）调整半导体部件（1）中的载流子寿命的工序中，在半导体部件（1）中产生至少两个缺陷区域（10,11,12,13）。 在该过程中，由具有至少大致相同的初始能量的粒子（a，b，c，d）组成的粒子束（P）在到达半导体部件（2）之前由至少一个装置（2）起作用 1），使得颗粒（a，b，c，d）随后具有不同的能量值，至少两个能量值组是可区分的。 因此，通过单粒子照射操作可以产生任意数量的排列和加权可任意选择的缺陷区域。

公开(公告)号：US08829571B2

公开(公告)日：2014-09-09

申请号：US13468593

申请日：2012-05-10

Applicant: Munaf Rahimo ,  Arnost Kopta ,  Jan Vobecky ,  Wolfgang Janisch

Inventor： Munaf Rahimo ,  Arnost Kopta ,  Jan Vobecky ,  Wolfgang Janisch

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/739

CPC classification number: H01L29/7395 ,  H01L29/0611 ,  H01L29/66333

Abstract: A maximum-punch-through semiconductor device such as an insulated gate bipolar transistor (IGBT) or a diode, and a method for producing same are disclosed. The MPT semiconductor device can include at least a two-layer structure having an emitter metallization, a channel region, a base layer with a predetermined doping concentration ND, a buffer layer and a collector metallization. A thickness W of the base layer can be determined by: W = V bd + V pt 4010 ⁢ ⁢ kV ⁢ ⁢ cm - 5 / 8 * ( N D ) 1 / 8 wherein a punch-through voltage Vpt of the semiconductor device is between 70% and 99% of a break down voltage Vbd of the semiconductor device, and wherein the thickness W is a minimum thickness of the base layer between a junction to the channel region and the buffer layer.

Abstract translation: 公开了诸如绝缘栅双极晶体管（IGBT）或二极管的最大穿通半导体器件及其制造方法。 MPT半导体器件可以包括具有发射极金属化的至少两层结构，沟道区，具有预定掺杂浓度ND的基极层，缓冲层和集电极金属化。 基底层的厚度W可以通过以下公式确定：W = V bd + V pt 4010注册kV电容cm -5 / 8 *（ND）1/8其中半导体器件的穿通电压Vpt在 70％和99％的半导体器件的击穿电压Vbd，并且其中厚度W是在结到通道区域与缓冲层之间的基底层的最小厚度。

公开(公告)号：US08450793B2

公开(公告)日：2013-05-28

申请号：US12753570

申请日：2010-04-02

Applicant: Munaf Rahimo ,  Jan Vobecky ,  Wolfgang Janisch ,  Arnost Kopta ,  Frank Ritchie

Inventor： Munaf Rahimo ,  Jan Vobecky ,  Wolfgang Janisch ,  Arnost Kopta ,  Frank Ritchie

IPC: H01L29/66

CPC classification number: H01L29/7395 ,  H01L29/0834

Abstract: A controlled-punch-through semiconductor device with a four-layer structure is disclosed which includes layers of different conductivity types, a collector on a collector side, and an emitter on an emitter side which lies opposite the collector side. The semiconductor device can be produced by a method performed in the following order: producing layers on the emitter side of wafer of a first conductivity type; thinning the wafer on a second side; applying particles of the first conductivity type to the wafer on the collector side for forming a first buffer layer having a first peak doping concentration in a first depth, which is higher than doping of the wafer; applying particles of a second conductivity type to the wafer on the second side for forming a collector layer on the collector side; and forming a collector metallization on the second side. At any stage particles of the first conductivity type can be applied to the wafer on the second side for forming a second buffer layer with a second peak doping concentration lower than the first peak doping concentration of the first buffer layer, but higher than the doping of the wafer. A third buffer layer can be arranged between the first depth and the second depth with a doping concentration which is lower than the second peak doping concentration of the second buffer layer. Thermal treatment can be used for forming the first buffer layer, the second buffer layer and/or the collector layer.

Abstract translation: 公开了具有四层结构的受控穿通半导体器件，其包括不同导电类型的层，集电极侧的集电极和位于集电极侧的发射极侧的发射极。 半导体器件可以通过以下顺序执行的方法制造：在第一导电类型的晶片的发射极侧产生层; 在第二面上稀薄晶片; 将第一导电类型的颗粒施加到集电极侧的晶片，以形成第一深度的第一峰值掺杂浓度高于晶片掺杂的第一缓冲层; 将第二导电类型的颗粒施加到第二侧上的晶片，以在集电极侧上形成集电极层; 以及在第二面上形成收集器金属化。 在任何阶段，可以将第一导电类型的颗粒施加到第二侧上的晶片，以形成具有低于第一缓冲层的第一峰掺杂浓度的第二峰值掺杂浓度的第二缓冲层，但高于掺杂 晶圆。 可以在第一深度和第二深度之间布置第三缓冲层，其掺杂浓度低于第二缓冲层的第二峰值掺杂浓度。 热处理可以用于形成第一缓冲层，第二缓冲层和/或集电体层。

公开(公告)号：US20110108953A1

公开(公告)日：2011-05-12

申请号：US12942410

申请日：2010-11-09

Applicant: Jan VOBECKY ,  Kati Hemmann ,  Hamit Duran ,  Munaf Rahimo

Inventor： Jan VOBECKY ,  Kati Hemmann ,  Hamit Duran ,  Munaf Rahimo

IPC: H01L29/00 ,  H01L21/22

CPC classification number: H01L29/8611 ,  H01L29/0661 ,  H01L29/32 ,  H01L29/36 ,  H01L29/66128

Abstract: A fast recovery diode includes an n-doped base layer having a cathode side and an anode side opposite the cathode side. A p-doped anode layer is arranged on the anode side. The anode layer has a doping profile and includes at least two sublayers. A first one of the sublayers has a first maximum doping concentration, which is between 2*1016 cm−3 and 2*1017 cm−3 and which is higher than the maximum doping concentration of any other sublayer. A last one of the sublayers has a last sublayer depth, which is larger than any other sublayer depth. The last sublayer depth is between 90 to 120 μm. The doping profile of the anode layer declines such that a doping concentration in a range of 5*1014 cm−3 and 1*1015 cm−3 is reached between a first depth, which is at least 20 μm, and a second depth, which is at maximum 50 μm. Such a profile of the doping concentration is achieved by using aluminium diffused layers as the at least two sublayers.

Abstract translation: 快速恢复二极管包括具有阴极侧和与阴极侧相对的阳极侧的n掺杂基极层。 p型掺杂阳极层设置在阳极侧。 阳极层具有掺杂分布并且包括至少两个子层。 第一个子层具有第一最大掺杂浓度，其在2×1016cm-3和2×1017cm-3之间，并且高于任何其它子层的最大掺杂浓度。 最后一个子层具有比任何其他子层深度大的最后一个子层深度。 最后的子层深度为90〜120μm。 阳极层的掺杂分布下降，使得在第一深度（至少20μm）和第二深度之间达到在5×10 14 cm -3和1×10 15 cm -3范围内的掺杂浓度，其中 最大为50μm。 通过使用铝扩散层作为至少两个子层来实现掺杂浓度的这种分布。

公开(公告)号：US20100244093A1

公开(公告)日：2010-09-30

申请号：US12753570

申请日：2010-04-02

Applicant: Munaf Rahimo ,  Jan Vobecky ,  Wolfgang Janisch ,  Arnost Kopta ,  Frank Ritchie

Inventor： Munaf Rahimo ,  Jan Vobecky ,  Wolfgang Janisch ,  Arnost Kopta ,  Frank Ritchie

IPC: H01L29/739 ,  H01L21/331

CPC classification number: H01L29/7395 ,  H01L29/0834

Abstract: A controlled-punch-through semiconductor device with a four-layer structure is disclosed which includes layers of different conductivity types, a collector on a collector side, and an emitter on an emitter side which lies opposite the collector side. The semiconductor device can be produced by a method performed in the following order: producing layers on the emitter side of wafer of a first conductivity type; thinning the wafer on a second side; applying particles of the first conductivity type to the wafer on the collector side for forming a first buffer layer having a first peak doping concentration in a first depth, which is higher than doping of the wafer; applying particles of a second conductivity type to the wafer on the second side for forming a collector layer on the collector side; and forming a collector metallization on the second side. At any stage particles of the first conductivity type can be applied to the wafer on the second side for forming a second buffer layer with a second peak doping concentration lower than the first peak doping concentration of the first buffer layer, but higher than the doping of the wafer. A third buffer layer can be arranged between the first depth and the second depth with a doping concentration which is lower than the second peak doping concentration of the second buffer layer. Thermal treatment can be used for forming the first buffer layer, the second buffer layer and/or the collector layer.

Abstract translation: 公开了具有四层结构的受控穿通半导体器件，其包括不同导电类型的层，集电极侧的集电极和位于集电极侧的发射极侧的发射极。 半导体器件可以通过以下顺序执行的方法制造：在第一导电类型的晶片的发射极侧产生层; 在第二面上稀薄晶片; 将第一导电类型的颗粒施加到集电极侧的晶片，以形成第一深度的第一峰值掺杂浓度高于晶片掺杂的第一缓冲层; 将第二导电类型的颗粒施加到第二侧上的晶片，以在集电极侧上形成集电极层; 以及在第二面上形成收集器金属化。 在任何阶段，可以将第一导电类型的颗粒施加到第二侧上的晶片，以形成具有低于第一缓冲层的第一峰掺杂浓度的第二峰值掺杂浓度的第二缓冲层，但高于掺杂 晶圆。 可以在第一深度和第二深度之间布置第三缓冲层，其掺杂浓度低于第二缓冲层的第二峰值掺杂浓度。 热处理可以用于形成第一缓冲层，第二缓冲层和/或集电体层。