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    METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE
    11.
    发明申请
    METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20130102114A1

    公开(公告)日：2013-04-25

    申请号：US13347361

    申请日：2012-01-10

    申请人： Song-Ju LEE ,  Jeong Soo Park ,  Byung-Gook Park ,  Hyun Woo Kim

    发明人： Song-Ju LEE ,  Jeong Soo Park ,  Byung-Gook Park ,  Hyun Woo Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66356 ,  H01L29/7391

    摘要： A technology is capable of simplifying a process of manufacturing an asymmetric device in forming a Tunneling Field Effect Transistor (TFET) structure. A method for manufacturing a semiconductor device comprises forming a conductive pattern over a semiconductor substrate, implanting impurity ions with the conductive pattern as a mask to form a first junction region in the semiconductor substrate, forming a first insulating film planarized with the conductive pattern over the first junction region, etching the top of the conductive pattern to expose a sidewall of the first insulating film, forming a spacer at the sidewall of the first insulating film disposed over the conductive pattern, etching the conductive pattern with the spacer as an etching mask to form a gate pattern, and forming a second junction region in the semiconductor substrate with the gate pattern as a mask.

    摘要翻译： 一种技术能够简化在形成隧道场效应晶体管（TFET）结构中制造非对称器件的工艺。 一种制造半导体器件的方法，包括在半导体衬底上形成导电图案，将导电图案作为掩模注入杂质离子，以在半导体衬底中形成第一结区，在导电图案上形成平坦化的第一绝缘膜， 第一接合区域，蚀刻导电图案的顶部以暴露第一绝缘膜的侧壁，在布置在导电图案上的第一绝缘膜的侧壁处形成间隔物，用间隔物蚀刻导电图案作为蚀刻掩模， 形成栅极图案，并且以栅极图案作为掩模在半导体衬底中形成第二结区域。

    Method of fabricating a semiconductor device
    12.
    发明授权
    Method of fabricating a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US06387759B1

    公开(公告)日：2002-05-14

    申请号：US09299577

    申请日：1999-04-27

    申请人： Jeong-Soo Park ,  Wouns Yang ,  Hyun-Jo Yang

    发明人： Jeong-Soo Park ,  Wouns Yang ,  Hyun-Jo Yang

    IPC分类号： H01L218234

    CPC分类号： H01L27/11517 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11551

    摘要： A method of fabricating semiconductor device is provided that includes a method of forming plugs in a semiconductor device. The plugs or contacts can connect an upper conductive layer to a lower conductive layer. The plugs are preferably formed without providing contact holes. The method of fabricating a semiconductor device can include the steps of defining an active area of a device by forming a field insulating layer on a semiconductor substrate of a first conductivity type, forming a gate oxide on an exposed surface of the active layer and forming a plurality of gates and associated cap insulating layers along a first direction perpendicular to an active area. An impurity region of a second conductivity type is formed in the exposed active area of the semiconductor substrate and a plurality of sidewall spacers are formed at sides of the gates. An electrically-conductive layer is formed for contacting the impurity region between the gates on the semiconductor substrate. The method can further include forming a plurality of plugs by patterning the electrically-conductive layer so that the plugs contact the impurity region, and an insulating interlayer is then formed where the plugs are not formed between the gates.

    摘要翻译： 提供一种制造半导体器件的方法，其包括在半导体器件中形成插塞的方法。 插头或触点可以将上导电层连接到下导电层。 塞子优选地形成而不提供接触孔。 制造半导体器件的方法可以包括以下步骤：通过在第一导电类型的半导体衬底上形成场绝缘层来限定器件的有源区，在有源层的暴露表面上形成栅极氧化物，并形成 多个栅极和相关联的帽绝缘层沿垂直于有效区域的第一方向。 在半导体衬底的暴露的有源区域中形成第二导电类型的杂质区域，并且在栅极的侧面形成多个侧壁间隔物。 形成用于接触半导体衬底上的栅极之间的杂质区的导电层。 该方法还可以包括通过使导电层图案化形成多个插塞，使得插头接触杂质区域，然后形成绝缘中间层，其中插塞未形成在栅极之间。

    Dual gate MOSFET fabrication method
    13.
    发明授权
    Dual gate MOSFET fabrication method 失效
    双栅MOSFET制造方法

    公开(公告)号：US06168998A

    公开(公告)日：2001-01-02

    申请号：US09243534

    申请日：1999-02-03

    申请人： Jeong-Soo Park

    发明人： Jeong-Soo Park

    IPC分类号： H01L21336

    CPC分类号： H01L21/82345

    摘要： A dual gate MOSFET fabrication method includes the steps of forming a first insulation layer on a semiconductor substrate, forming a first polysilicon layer on the first insulation layer, forming a first photoresist pattern on the first polysilicon layer, forming a first gate by sequentially etching the first polysilicon layer and the first insulation layer by using the first photoresist pattern as a mask, removing the first photoresist pattern, forming a second insulation layer on the semiconductor substrate and the first gate, forming a second polysilicon layer on the second insulation layer, forming a second photoresist pattern on the second polysilicon layer, and forming a second gate by etching the second polysilicon layer and the second insulation layer by using the second photoresist pattern as a mask.

    摘要翻译： 双栅极MOSFET制造方法包括以下步骤：在半导体衬底上形成第一绝缘层，在第一绝缘层上形成第一多晶硅层，在第一多晶硅层上形成第一光致抗蚀剂图案，通过依次蚀刻第 第一多晶硅层和第一绝缘层，通过使用第一光致抗蚀剂图案作为掩模，去除第一光致抗蚀剂图案，在半导体衬底和第一栅极上形成第二绝缘层，在第二绝缘层上形成第二多晶硅层，形成 第二多晶硅层上的第二光致抗蚀剂图案，并且通过使用第二光致抗蚀剂图案作为掩模，通过蚀刻第二多晶硅层和第二绝缘层来形成第二栅极。

    Sub-word line driver circuit and semiconductor memory device having the same
    15.
    发明授权
    Sub-word line driver circuit and semiconductor memory device having the same 有权
    子字线驱动电路和半导体存储器件

    公开(公告)号：US08279703B2

    公开(公告)日：2012-10-02

    申请号：US12839454

    申请日：2010-07-20

    申请人： Hyang-Ja Yang ,  Jeong-Soo Park

    发明人： Hyang-Ja Yang ,  Jeong-Soo Park

    IPC分类号： G11C8/00 ,  H01L29/76 ,  H01L21/70

    CPC分类号： G11C8/08

    摘要： A sub-word line driver includes a substrate, a plurality of gate lines and at least one gate tab. The substrate includes a plurality of isolation areas and a plurality of active areas, where the two active areas are separated by each isolation area, and the isolation areas and the active areas are extended in a first direction and are arranged in a second direction perpendicular to the first direction. The plurality of gate lines are formed on the substrate, where the gate lines are extended in a second direction and are arranged in the first direction. The at least one gate tab is formed on the substrate, where the at least one gate tab is extended in the first direction to cover the isolation area. Incorrect operation of the sub-word line driver may be prevented, and a power consumption of the sub-word line driver may be reduced.

    摘要翻译： 子字线驱动器包括衬底，多个栅极线和至少一个栅极突起。 衬底包括多个隔离区域和多个有效区域，其中两个有源区域由每个隔离区域分开，并且隔离区域和有源区域在第一方向上延伸并且沿垂直于 第一个方向。 多个栅极线形成在基板上，其中栅极线沿第二方向延伸并且沿第一方向布置。 所述至少一个栅极突片形成在所述基板上，其中所述至少一个栅极突片在所述第一方向上延伸以覆盖所述隔离区域。 可以防止子字线驱动器的不正确的操作，并且可以减少子字线驱动器的功耗。

    Image processing apparatus and method
    16.
    发明申请
    Image processing apparatus and method 有权
    图像处理装置及方法

    公开(公告)号：US20120075287A1

    公开(公告)日：2012-03-29

    申请号：US13067515

    申请日：2011-06-06

    申请人： Chan Min Park ,  Tack Don Han ,  Jeong Soo Park ,  Jae Ho Nah ,  Yun Hye Jung

    发明人： Chan Min Park ,  Tack Don Han ,  Jeong Soo Park ,  Jae Ho Nah ,  Yun Hye Jung

    IPC分类号： G06T15/00

    CPC分类号： G06T15/06

    摘要： Provided is an image processing apparatus. The image processing apparatus may perform an intersection test for rendering of a ray tracing scheme. The image processing apparatus may include a first calculator and a second calculator. The first calculator may perform a ray-plane test to determine whether a ray intersects a plane including a primitive and a barycentric test to determine whether the ray intersects the primitive. The second calculator may calculate a hit point based on the ray which intersects the primitive.

    摘要翻译： 提供了一种图像处理装置。 图像处理装置可以执行用于渲染光线跟踪方案的交叉测试。 图像处理装置可以包括第一计算器和第二计算器。 第一计算器可以执行射线平面测试以确定射线是否与包括原始和重心测试的平面相交，以确定射线是否与原始物相交。 第二计算器可以基于与原语相交的射线计算命中点。

    Image processing apparatus and method
    17.
    发明申请
    Image processing apparatus and method 有权
    图像处理装置及方法

    公开(公告)号：US20120050289A1

    公开(公告)日：2012-03-01

    申请号：US13067733

    申请日：2011-06-22

    申请人： Chan Min Park ,  Tack Don Han ,  Jin Woo Kim ,  Jeong Soo Park ,  Jae Ho Nah

    发明人： Chan Min Park ,  Tack Don Han ,  Jin Woo Kim ,  Jeong Soo Park ,  Jae Ho Nah

    IPC分类号： G06T15/50 ,  G06T15/00

    CPC分类号： G06T15/06 ,  G06T17/005

    摘要： An image processing apparatus is provided. A splitting unit of the image processing apparatus may split a first space within an input three-dimensional (3D) model into a plurality of subspaces in order to generate an acceleration structure of the input 3D model. A decision unit of the image processing apparatus may set a subspace determined as having a relatively high probability of including a ray progress path among the plurality of subspaces, as a child node having a relatively high traversal priority in the acceleration structure among a plurality of child nodes.

    摘要翻译： 提供一种图像处理装置。 图像处理装置的分割单元可以将输入三维（3D）模型内的第一空间分割成多个子空间，以便生成输入3D模型的加速结构。 图像处理装置的判定单元可以将在多个子空间中包括射线进入路径的相对较高概率的子空间设置为多个孩子中的加速结构中具有较高遍历优先级的子节点 节点。