公开(公告)号：US20110064137A1

公开(公告)日：2011-03-17

申请号：US12861118

申请日：2010-08-23

Applicant: Jin Ho Han ,  Seong Mo Park ,  Nak Woong Eum

Inventor： Jin Ho Han ,  Seong Mo Park ,  Nak Woong Eum

IPC: H04N7/50 ,  H04N7/26

CPC classification number: H04N19/53 ,  H04N19/194 ,  H04N19/43 ,  H04N19/433 ,  H04N19/61

Abstract: There is provided a video encoding apparatus allowing for enhanced video encoding speed according to the H.264 video coding standard. The video encoding apparatus allows the memories included in the video encoding apparatus to be shared by a plurality of elements through the rearrangement and the structural change of the memories considering an efficient hierarchical motion estimation algorithm. Therefore, the video encoding apparatus has the effects of reducing the amount of transmitted and received data between the frame memory and the video encoding apparatus and enhancing video encoding speed.

Abstract translation: 提供了根据H.264视频编码标准允许增强的视频编码速度的视频编码装置。 视频编码装置允许考虑到有效的分级运动估计算法，通过重排和存储器的结构变化，包括在视频编码装置中的存储器被多个元件共享。 因此，视频编码装置具有减少帧存储器和视频编码装置之间的发送和接收数据量并提高视频编码速度的效果。

公开(公告)号：US08514937B2

公开(公告)日：2013-08-20

申请号：US12861118

申请日：2010-08-23

Applicant: Jin Ho Han ,  Seong Mo Park ,  Nak Woong Eum

Inventor： Jin Ho Han ,  Seong Mo Park ,  Nak Woong Eum

IPC: H04N7/50

CPC classification number: H04N19/53 ,  H04N19/194 ,  H04N19/43 ,  H04N19/433 ,  H04N19/61

Abstract: There is provided a video encoding apparatus allowing for enhanced video encoding speed according to the H.264 video coding standard. The video encoding apparatus allows the memories included in the video encoding apparatus to be shared by a plurality of elements through the rearrangement and the structural change of the memories considering an efficient hierarchical motion estimation algorithm. Therefore, the video encoding apparatus has the effects of reducing the amount of transmitted and received data between the frame memory and the video encoding apparatus and enhancing video encoding speed.

Abstract translation: 提供了根据H.264视频编码标准允许增强的视频编码速度的视频编码装置。 视频编码装置允许考虑到有效的分级运动估计算法，通过重排和存储器的结构变化，包括在视频编码装置中的存储器被多个元件共享。 因此，视频编码装置具有减少帧存储器和视频编码装置之间的发送和接收数据量并提高视频编码速度的效果。

公开(公告)号：US08139643B2

公开(公告)日：2012-03-20

申请号：US12191733

申请日：2008-08-14

Applicant: Jin Ho Han ,  Suk Ho Lee ,  Seong Mo Park ,  Nak Woong Eum

Inventor： Jin Ho Han ,  Suk Ho Lee ,  Seong Mo Park ,  Nak Woong Eum

IPC: H04B1/66

CPC classification number: H04N19/523 ,  H04N19/43

Abstract: Provided is a motion estimation apparatus for moving picture coding. The apparatus includes a 1-pel buffer for storing 1-pel unit pixels using luminance signals of a reference frame which correspond to macroblocks of a current frame, a 1-pel estimator for calculating 1-pel unit motion vectors and minimum costs in correspondence to the macroblocks of the current frame and the pixels stored in the 1-pel buffer, a ½-pel interpolator for performing ½-pel unit interpolation using the pixels stored in the 1-pel buffer, a ½-pel buffer for storing the ½-pel unit interpolated pixels, a ½-pel estimator for calculating ½-pel unit motion vectors and minimum costs in correspondence to the pixels stored in the ½-pel buffer, the values calculated by the 1-pel estimator, and the macroblocks of the current frame, a ¼-pel interpolator for performing ¼-pel unit interpolation using the pixels stored in the ½-pel and 1-pel buffers, a ¼-pel buffer for storing the ¼-pel unit interpolated pixels, and a ¼-pel estimator for calculating ¼-pel unit motion vectors and minimum costs in correspondence to the pixels stored in the ¼-pel buffer, the values calculated by the ½-pel estimator, and the macroblocks of the current frame.

Abstract translation: 提供了一种用于运动图像编码的运动估计装置。 该装置包括：1个像素缓冲器，用于使用与当前帧的宏块相对应的参考帧的亮度信号来存储1个像素单位像素; 1像素估计器，用于计算1像素单位运动矢量，并对应于最小成本 当前帧的宏块和存储在1-像素缓冲器中的像素，1/2像素内插器，用于使用存储在1-像素缓冲器中的像素进行1/2像素单位内插;½像素缓冲器，用于存储1/2像素缓冲器， 像素单位内插像素，用于计算1/2像素单位运动矢量的1/2像素估计器和对应于存储在1/2像素缓冲器中的像素的最小成本，由1-像素估计器计算的值和当前的宏块 帧，¼贝尔内插器，用于使用存储在1/2贝尔和1贝尔缓冲器中的像素执行1/4贝尔单位内插，用于存储1/4倍率单位内插像素的1/4贝尔缓冲器，以及1/4贝尔估计器 用于计算¼像素单位运动矢量 对应于存储在1/4贝尔缓冲器中的像素的最小成本，由1/2贝尔估计器计算的值和当前帧的宏块。

公开(公告)号：US07711787B2

公开(公告)日：2010-05-04

申请号：US11300731

申请日：2005-12-14

Applicant: Jin Ho Han ,  Young Hwan Bae ,  Han Jin Cho ,  Jun Young Chang

Inventor： Jin Ho Han ,  Young Hwan Bae ,  Han Jin Cho ,  Jun Young Chang

IPC: G06F15/16

CPC classification number: H04L49/10 ,  H04L49/109 ,  H04L49/3009 ,  H04L49/3018 ,  H04L49/503

Abstract: An on-chip network interfacing apparatus and method are provided. The apparatus includes a plurality of on-chip network ports; a switch receiving data from a first on-chip network port of the on-chip network ports and transmitting the received data to a second on-chip network port of the on-chip network ports; and an interface unit interfacing an advanced microcontroller bus architecture (AMBA) signal received from an module, which is designed according to an AMBA on-chip bus protocol, and outputting the interfacing result to the first on-chip network port; and interfacing the on-chip network signal received from the first on-chip network port, and outputting the interfacing result to the module. Accordingly, it is possible to establish communications at increased speeds by interfacing a signal according to the AMBA 2.0 on-chip bus protocol with a signal according to the on-chip network protocol.

Abstract translation: 提供了片上网络接口设备和方法。 该装置包括多个片上网络端口; 从所述片上网络端口的第一片上网络端口接收数据并将所接收的数据发送到所述片上网络端口的第二片上网络端口; 以及接口单元，其连接从根据AMBA片上总线协议设计的模块接收的高级单片机总线架构（AMBA）信号，并将所述接口结果输出到所述第一片上网络端口; 并且连接从第一片上网络端口接收的片上网络信号，并将接口结果输出到模块。 因此，可以通过将根据AMBA 2.0片上总线协议的信号与根据片上网络协议的信号进行接口来以增加的速度建立通信。

公开(公告)号：US07432768B2

公开(公告)日：2008-10-07

申请号：US10572901

申请日：2004-06-22

Applicant: Seon Ho Han ,  Jin Ho Han ,  Mun Yang Park

Inventor： Seon Ho Han ,  Jin Ho Han ,  Mun Yang Park

IPC: H03L7/00

CPC classification number: H03B5/1841 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/124 ,  H03B5/1265 ,  H03B5/1293

Abstract: Provided are a voltage controlled digital analog oscillator and a frequency synthesizer using the same, the oscillator comprising an oscillator having a frequency of an output signal being determined by a voltage inputted to an analog input end and a digital value inputted to a digital input end; and a digital tuner for comparing the voltage inputted to the analog input end to first and second threshold voltages and changing the digital value inputted to the digital input end according to the result, whereby it is possible to obtain a broadband frequency output with less noise.

Abstract translation: 提供一种电压控制数字模拟振荡器和使用该振荡器的频率合成器，该振荡器包括具有由输入到模拟输入端的电压和输入到数字输入端的数字值确定输出信号频率的振荡器; 以及数字调谐器，用于将输入到模拟输入端的电压与第一和第二阈值电压进行比较，并根据结果改变输入到数字输入端的数字值，由此可以获得具有较小噪声的宽带频率输出。

公开(公告)号：US20080082621A1

公开(公告)日：2008-04-03

申请号：US11861360

申请日：2007-09-26

Applicant: Jin-Ho HAN ,  Han-Jin CHO

Inventor： Jin-Ho HAN ,  Han-Jin CHO

IPC: G06F15/173

CPC classification number: G06F15/16

Abstract: There is provided a slave network interface circuit for improving the parallelism of an On-Chip network, including: a MUX for selecting one of a Write Address inputted from the On-Chip network and a Read Address to read data from a slave module, which is inputted from a slave network interface (SNI) controller, in response to the control of the SNI controller and inputs the selected address to the slave module; and the SNI controller for controlling writing and reading data at the slave module and generating a Read Address to store data read from the slave module and to transfer to the On-Chip network.

Abstract translation: 提供了一种用于提高片上网络的并行性的从属网络接口电路，包括：用于选择从片上网络输入的写地址中的一个的MUX和从从模块读取数据的读地址， 响应于SNI控制器的控制并将选择的地址输入到从模块，从从网络接口（SNI）控制器输入; 以及用于控制在从模块处的写入和读取数据的SNI控制器，并产生读地址以存储从从模块读取的数据并传送到片上网络。

公开(公告)号：US20070030080A1

公开(公告)日：2007-02-08

申请号：US10572901

申请日：2004-06-22

Applicant: Seon Ho Han ,  Jin Ho Han ,  Mun Yang Park

Inventor： Seon Ho Han ,  Jin Ho Han ,  Mun Yang Park

IPC: H03L7/00

CPC classification number: H03B5/1841 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/124 ,  H03B5/1265 ,  H03B5/1293

Abstract: Provided are a voltage controlled digital analog oscillator and a frequency synthesizer using the same, the oscillator comprising an oscillator having a frequency of an output signal being determined by a voltage inputted to an analog input end and a digital value inputted to a digital input end; and a digital tuner for comparing the voltage inputted to the analog input end to first and second threshold voltages and changing the digital value inputted to the digital input end according to the result, whereby it is possible to obtain a broadband frequency output with less noise.

Abstract translation: 提供一种电压控制数字模拟振荡器和使用该振荡器的频率合成器，该振荡器包括具有由输入到模拟输入端的电压和输入到数字输入端的数字值确定输出信号频率的振荡器; 以及数字调谐器，用于将输入到模拟输入端的电压与第一和第二阈值电压进行比较，并根据结果改变输入到数字输入端的数字值，由此可以获得具有较小噪声的宽带频率输出。