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    Switch block circuit in field programmable gate array
    1.
    发明授权
    Switch block circuit in field programmable gate array 有权
    现场可编程门阵列中的开关块电路

    公开(公告)号：US08890570B2

    公开(公告)日：2014-11-18

    申请号：US13607637

    申请日：2012-09-07

    Applicant: Han Jin Cho ,  Young Hwan Bae

    Inventor： Han Jin Cho ,  Young Hwan Bae

    IPC: H01L25/00 ,  H03K19/173 ,  G11C5/06

    CPC classification number: H03K19/17744 ,  H03K19/1737 ,  H03K19/1776

    Abstract: A switch block circuit in a field programmable gate array is provided. The switch block circuit includes a configuration memory unit including first group memories and second group memories and a switching unit including first group switching transistors and second group switching transistors. The switch block circuit further includes a selection unit for correspondingly connecting the second group memories with the second group switching transistors depending on an operation mode. The switch block is efficiently reconfigurable depending on the intended use, and configuration memories unused in a specific operation mode may be applied to other purposes.

    Abstract translation: 提供现场可编程门阵列中的开关块电路。 开关块电路包括配置存储单元，其包括第一组存储器和第二组存储器，以及包括第一组开关晶体管和第二组开关晶体管的开关单元。 开关块电路还包括用于根据操作模式相应地将第二组存储器与第二组开关晶体管连接的选择单元。 切换块根据预期用途有效地可重新配置，并且在特定操作模式中未使用的配置存储器可以应用于其他目的。

    On-chip network interfacing apparatus and method
    3.
    发明授权
    On-chip network interfacing apparatus and method 有权
    片上网络接口设备及方法

    公开(公告)号：US07711787B2

    公开(公告)日：2010-05-04

    申请号：US11300731

    申请日：2005-12-14

    Applicant: Jin Ho Han ,  Young Hwan Bae ,  Han Jin Cho ,  Jun Young Chang

    Inventor： Jin Ho Han ,  Young Hwan Bae ,  Han Jin Cho ,  Jun Young Chang

    IPC: G06F15/16

    CPC classification number: H04L49/10 ,  H04L49/109 ,  H04L49/3009 ,  H04L49/3018 ,  H04L49/503

    Abstract: An on-chip network interfacing apparatus and method are provided. The apparatus includes a plurality of on-chip network ports; a switch receiving data from a first on-chip network port of the on-chip network ports and transmitting the received data to a second on-chip network port of the on-chip network ports; and an interface unit interfacing an advanced microcontroller bus architecture (AMBA) signal received from an module, which is designed according to an AMBA on-chip bus protocol, and outputting the interfacing result to the first on-chip network port; and interfacing the on-chip network signal received from the first on-chip network port, and outputting the interfacing result to the module. Accordingly, it is possible to establish communications at increased speeds by interfacing a signal according to the AMBA 2.0 on-chip bus protocol with a signal according to the on-chip network protocol.

    Abstract translation: 提供了片上网络接口设备和方法。 该装置包括多个片上网络端口; 从所述片上网络端口的第一片上网络端口接收数据并将所接收的数据发送到所述片上网络端口的第二片上网络端口; 以及接口单元，其连接从根据AMBA片上总线协议设计的模块接收的高级单片机总线架构（AMBA）信号，并将所述接口结果输出到所述第一片上网络端口; 并且连接从第一片上网络端口接收的片上网络信号，并将接口结果输出到模块。 因此，可以通过将根据AMBA 2.0片上总线协议的信号与根据片上网络协议的信号进行接口来以增加的速度建立通信。

    SWITCH APPARATUS FOR FIELD PROGRAMMABLE GATE ARRAY
    4.
    发明申请
    SWITCH APPARATUS FOR FIELD PROGRAMMABLE GATE ARRAY 审中-公开
    用于现场可编程门阵列的开关装置

    公开(公告)号：US20120161813A1

    公开(公告)日：2012-06-28

    申请号：US13305446

    申请日：2011-11-28

    Applicant: Han Jin CHO ,  Young Hwan BAE

    Inventor： Han Jin CHO ,  Young Hwan BAE

    IPC: H03K19/177

    CPC classification number: H03K19/17748 ,  H03K19/0008

    Abstract: A switch apparatus of a Field Programmable Gate Array (FPGA) includes a pass transistor configured to switch and transfer an input signal to a logic cell according to a value of a configuration memory, and a voltage maintaining unit connected between the configuration memory and a gate of the pass transistor and configured to delay a drop of a gate voltage.

    Abstract translation: 现场可编程门阵列（FPGA）的开关装置包括：传输晶体管，被配置为根据配置存储器的值来切换输入信号并将其传送到逻辑单元;以及电压保持单元，连接在配置存储器和门 并且被配置为延迟栅极电压的下降。

    METHOD FOR SYNTHESIZING TILE INTERCONNECTION STRUCTURE OF FIELD PROGRAMMABLE GATE ARRAY
    5.
    发明申请
    METHOD FOR SYNTHESIZING TILE INTERCONNECTION STRUCTURE OF FIELD PROGRAMMABLE GATE ARRAY 审中-公开
    合成现场可编程门阵列的层间互连结构的方法

    公开(公告)号：US20120167023A1

    公开(公告)日：2012-06-28

    申请号：US13310580

    申请日：2011-12-02

    Applicant: Young Hwan BAE

    Inventor： Young Hwan BAE

    IPC: G06F17/50

    CPC classification number: G06F17/5054 ,  G06F17/5077

    Abstract: A method for synthesizing a tile interconnection structure of a field programmable gate array (FPGA) includes: receiving an interconnection structure specification of the FPGA; constructing a tile interconnection graph based on the interconnection structure specification; converting the interconnection structure specification into a connection diagram between two points on the tile interconnection graph; searching for a shortest path for connection requirements between two points from the connection diagram between two points, and building a bundle structure; and synthesizing a tile interconnection structure from the bundle structure.

    Abstract translation: 一种用于合成现场可编程门阵列（FPGA）的瓦片互连结构的方法包括：接收FPGA的互连结构规范; 基于互连结构规范构建瓦片互连图; 将互连结构规范转换为瓦片互连图上两点之间的连接图; 从两点之间的连接图中搜索两点之间的连接要求的最短路径，并构建捆绑结构; 以及从所述束结构合成瓦片互连结构。

    ANISOTROPIC DIFFUSION METHOD AND APPARATUS BASED ON DIRECTION OF EDGE
    6.
    发明申请
    ANISOTROPIC DIFFUSION METHOD AND APPARATUS BASED ON DIRECTION OF EDGE 审中-公开
    基于边缘方向的各向异性扩散方法和装置

    公开(公告)号：US20100111438A1

    公开(公告)日：2010-05-06

    申请号：US12612055

    申请日：2009-11-04

    Applicant: June Young Chang ,  Han Jin Cho ,  Young Hwan Bae ,  Won Jong Kim ,  Mi Young Lee ,  Ju Yeob Kim ,  Guee Sang Lee ,  In San Jeon

    Inventor： June Young Chang ,  Han Jin Cho ,  Young Hwan Bae ,  Won Jong Kim ,  Mi Young Lee ,  Ju Yeob Kim ,  Guee Sang Lee ,  In San Jeon

    IPC: G06K9/40

    CPC classification number: G06T5/002 ,  G06T5/20 ,  G06T2207/20012 ,  G06T2207/20192

    Abstract: An anisotropic diffusion method and apparatus based on the direction of an edge are disclosed. In the anisotropic diffusion apparatus, directional pattern masking is performed to determine the direction of an edge in an image including noise, and values obtained through the directional pattern masking are convoluted to calculate the magnitude of an image. If the calculated magnitude value of the edge is larger than a threshold value, the edge of the image is preserved, while if the calculated magnitude value of the edge is not larger than the threshold value, noise cancellation is strengthened, whereby noise can be effectively canceled (or concealed) while preserving the edge representing the characteristics of the image, and thus, an image of high quality can be obtained.

    Abstract translation: 公开了一种基于边缘方向的各向异性扩散方法和装置。 在各向异性扩散装置中，执行方向图案掩蔽以确定包括噪声的图像中的边缘的方向，并且通过方向图案掩模获得的值被卷积以计算图像的大小。 如果边缘的计算幅度值大于阈值，则图像的边缘被保留，而如果所计算的边缘的幅度值不大于阈值，则噪声消除被加强，从而可以有效地产生噪声 取消（或隐藏），同时保留表示图像特征的边缘，从而可以获得高质量的图像。

    SWITCH BLOCK CIRCUIT IN FIELD PROGRAMMABLE GATE ARRAY
    7.
    发明申请
    SWITCH BLOCK CIRCUIT IN FIELD PROGRAMMABLE GATE ARRAY 有权
    现场可编程门阵列中的开关块电路

    公开(公告)号：US20130147516A1

    公开(公告)日：2013-06-13

    申请号：US13607637

    申请日：2012-09-07

    Applicant: Han Jin CHO ,  Young Hwan Bae

    Inventor： Han Jin CHO ,  Young Hwan Bae

    IPC: H03K19/177

    CPC classification number: H03K19/17744 ,  H03K19/1737 ,  H03K19/1776

    Abstract: A switch block circuit in a field programmable gate array is provided. The switch block circuit includes a configuration memory unit including first group memories and second group memories and a switching unit including first group switching transistors and second group switching transistors. The switch block circuit further includes a selection unit for correspondingly connecting the second group memories with the second group switching transistors depending on an operation mode. The switch block is efficiently reconfigurable depending on the intended use, and configuration memories unused in a specific operation mode may be applied to other purposes.

    Abstract translation: 提供现场可编程门阵列中的开关块电路。 开关块电路包括配置存储单元，其包括第一组存储器和第二组存储器，以及包括第一组开关晶体管和第二组开关晶体管的开关单元。 开关块电路还包括用于根据操作模式相应地将第二组存储器与第二组开关晶体管连接的选择单元。 切换块根据预期用途有效地可重新配置，并且在特定操作模式中未使用的配置存储器可以应用于其他目的。

    CONFIGURATION MEMORY APPARATUS IN FPGA AND ROUTER SYSTEM USING THE SAME
    8.
    发明申请
    CONFIGURATION MEMORY APPARATUS IN FPGA AND ROUTER SYSTEM USING THE SAME 审中-公开
    使用FPGA和路由器系统中的配置存储器设备

    公开(公告)号：US20110149984A1

    公开(公告)日：2011-06-23

    申请号：US12961752

    申请日：2010-12-07

    Applicant: Han Jin CHO ,  Young Hwan Bae

    Inventor： Han Jin CHO ,  Young Hwan Bae

    IPC: H04L12/56 ,  G11C7/10

    CPC classification number: H03K19/177

    Abstract: Disclosed are a configuration memory apparatus and a router system using the same. The configuration memory apparatus includes: a selection unit selecting one of a first external device and a storage unit and receiving data; a register storing input data received from the selection unit; a storage unit storing data received from the register; and an I/O unit controlling transmission and reception of data to and from the register and a second external device.

    Abstract translation: 公开了一种配置存储装置和使用该配置存储装置的路由器系统。 配置存储装置包括：选择单元，选择第一外部设备和存储单元中的一个并接收数据; 存储从所述选择单元接收的输入数据的寄存器; 存储单元，存储从寄存器接收的数据; 以及I / O单元，用于控制向寄存器和从第二外部设备发送和接收数据的I / O单元。

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