公开(公告)号：US08196471B2

公开(公告)日：2012-06-12

申请号：US11909293

申请日：2006-03-24

Applicant: Jin Ho Han ,  Dong Hyun Kim ,  In Seong Song

Inventor： Jin Ho Han ,  Dong Hyun Kim ,  In Seong Song

IPC: G01N29/00 ,  A61B8/14

CPC classification number: A61B8/12 ,  A61B8/4461

Abstract: The present invention relates to an ultrasonic probe for producing a real-time three dimensional live action image (a four dimensional image), which has a long lifetime, and an improved image quality, can prevent malfunction. The ultrasonic probe for producing a four dimensional image includes power transmission means for transmission of power from an upright motor to a module (2) having acoustic elements for swinging the module, the power transmission means includes a first link (20) having a horizontal portion (22) directly connected to a motor shaft, and a sloped portion projected upward from one side end of the horizontal portion at an angle in conformity with a locus of a swing action of the module, and a second link (21) comprising a horizontal (29) having an interlocking connected thereto and a pair of parallel portion (30) and (31) projected upwardly from opposite ends of the horizontal portion, such that the second link is interlocked along the first link in a state of being interposed between the first link and the module, wherein the interlocking shaft (28) is connected with an inclined portion of the first link by a shaft and the pair of parallel portions is mounting to a lower side of the module in a horizontal direction with a shaft.

Abstract translation: 本发明涉及一种用于制造具有长寿命和改进的图像质量的实时三维实况动作图像（四维图像）的超声波探头，可以防止故障。 用于产生四维图像的超声波探头包括用于将功率从直立马达传输到具有用于摆动模块的声学元件的模块（2）的动力传递装置，动力传递装置包括具有水平部分的第一连杆 （22），以及从所述水平部的一侧端部向与所述模块的摆动动作的轨迹一致的角度向上突出的倾斜部，以及包括水平方向的第二连杆（21） （29）和从所述水平部分的相对端部向上突出的一对平行部分（30）和（31），使得所述第二连杆沿着所述第一连杆以处于所述水平部分之间的状态互锁 第一连杆和模块，其中联锁轴（28）通过轴与第一连杆的倾斜部分连接，并且该对平行部分安装到模块的下侧 e在水平方向与轴。

公开(公告)号：US20120131356A1

公开(公告)日：2012-05-24

申请号：US13207484

申请日：2011-08-11

Applicant: Jin Ho HAN

Inventor： Jin Ho HAN

IPC: G06F1/26

CPC classification number: G06F1/324 ,  G06F1/26 ,  Y02D10/126

Abstract: The present invention relates to an apparatus for controlling power of mufti core processor, which includes a power control device by core unit, controls a plurality of power-related parameters by core unit, and thus decreases a load for power management and enables realization of a low power multi core processor through minute power control. The apparatus includes a processor core adapted to provide code information on an application program for executing to a power regulation controller, and a power regulation controller adapted to receive the code information on the application program from the processor core to determine an operation frequency of the processor core, set an operation voltage, a clock-gating value and a power-gating value according to the determined operation frequency, and provide the set values and voltage to the processor core.

Abstract translation: 本发明涉及一种用于控制核心处理器的功率的装置，其包括核心单元的功率控制装置，通过核心单元控制多个与功率有关的参数，从而减少用于电力管理的负载，并且能够实现 低功耗多核处理器，通过微功率控制。 所述设备包括处理器核心，其适于提供关于用于执行功率调节控制器的应用程序的代码信息;以及功率调节控制器，其适于从所述处理器核心接收关于所述应用程序的代码信息，以确定所述处理器的操作频率 根据所确定的工作频率设置工作电压，时钟门控值和电源门控值，并将设定值和电压提供给处理器核心。

公开(公告)号：US07916720B2

公开(公告)日：2011-03-29

申请号：US11861360

申请日：2007-09-26

Applicant: Jin-Ho Han ,  Han-Jin Cho

Inventor： Jin-Ho Han ,  Han-Jin Cho

IPC: H04L12/28

CPC classification number: G06F15/16

Abstract: There is provided a slave network interface circuit for improving the parallelism of an On-Chip network, including: a MUX for selecting one of a Write Address inputted from the On-Chip network and a Read Address to read data from a slave module, which is inputted from a slave network interface (SNI) controller, in response to the control of the SNI controller and inputs the selected address to the slave module; and the SNI controller for controlling writing and reading data at the slave module and generating a Read Address to store data read from the slave module and to transfer to the On-Chip network.

Abstract translation: 提供了一种用于提高片上网络的并行性的从属网络接口电路，包括：用于选择从片上网络输入的写地址中的一个的MUX和从从模块读取数据的读地址， 响应于SNI控制器的控制并将选择的地址输入到从模块，从从网络接口（SNI）控制器输入; 以及用于控制在从模块处的写入和读取数据的SNI控制器，并产生读地址以存储从从模块读取的数据并传送到片上网络。

公开(公告)号：US20090103625A1

公开(公告)日：2009-04-23

申请号：US12252734

申请日：2008-10-16

Applicant: Suk Ho Lee ,  Kyoung Seon Shin ,  Jin Ho Han ,  Seong Mo Park ,  Nak Woong Eum

Inventor： Suk Ho Lee ,  Kyoung Seon Shin ,  Jin Ho Han ,  Seong Mo Park ,  Nak Woong Eum

IPC: H04N7/26

CPC classification number: H04N19/436

Abstract: A video encoding apparatus and method using a pipeline technique with a variable time slot are provided. More particularly, a video encoding apparatus and method capable of shortening a video encoding time by variably adjusting lengths of time slots when an H.264 video encoding process is performed in a pipeline structure are provided. The video encoding apparatus includes a plurality of functional blocks that perform video encoding steps based on an H.264 standard for macroblocks configuring input digital video signals in a pipeline structure, and a controller that controls lengths of time slots configuring the pipeline structure based on done signals received from the plurality of functional blocks. Lengths of time slots can be adjusted according to operation times of video encoding steps using done signals generated from functional blocks, thereby preventing unnecessary power consumption and delays when using a fixed-length time slot.

Abstract translation: 提供了使用具有可变时隙的流水线技术的视频编码装置和方法。 更具体地说，提供了一种视频编码装置和方法，其能够在流水线结构中执行H.264视频编码处理时，通过可变地调整时隙的长度来缩短视频编码时间。 视频编码装置包括：多个功能块，其基于用于在流水线结构中配置输入数字视频信号的宏块的H.264标准执行视频编码步骤;以及控制器，其基于完成来控制配置流水线结构的时隙的长度 从多个功能块接收的信号。 可以根据从功能块产生的完成信号的视频编码步骤的操作时间来调整时隙长度，从而在使用固定长度的时隙时防止不必要的功耗和延迟。

公开(公告)号：US06870434B2

公开(公告)日：2005-03-22

申请号：US10464735

申请日：2003-06-19

Applicant: Jin Ho Han ,  Myung Shin Kwark ,  Jong Dae Kim

Inventor： Jin Ho Han ,  Myung Shin Kwark ,  Jong Dae Kim

IPC: H03B5/32 ,  H03B5/04 ,  H03B5/36 ,  H03L1/02

CPC classification number: H03L1/026

Abstract: The present invention relates to a method for compensating temperature in a crystal oscillator including a capacitor array consisted of a first bank of unit capacitors each with low capacitance and a second bank of unit capacitors each with high capacitance. The method comprising the steps of calculating memory address that stores information about the capacitor array address in accordance with the temperature that is subtracted from present temperature by a temperature offset code; reading data from a memory address corresponding to remain bits excepted lowest bit when the lowest bit is 0 among the memory address; averaging data read from a memory address corresponding to remain bits excepted lowest bit and data of a memory address incremented by 1 from the memory address when the lowest bit is 1 among the memory address; transmitting data read from the memory address or averaged data to the first bank or second bank by comparing the memory address and temperature boundary code; and adjusting the capacitor array with capacitance corresponding to a present temperature by using data transmitted to the first bank or second bank.

Abstract translation: 本发明涉及一种用于补偿晶体振荡器中的温度的方法，该晶体振荡器包括由具有低电容的第一组单位电容器组成的电容器阵列和具有高电容的第二组单位电容器。 该方法包括以下步骤：根据从当前温度减去温度偏移代码的温度计算存储关于电容器阵列地址的信息的存储器地址; 从存储器地址中的最低位为0时，从与除了最低位之外的保持位相对应的存储器地址读取数据; 从存储器地址中的最低位为1时，从存储器地址递增1的存储器地址中除了除了最低位之外的保留位和存储器地址的数据读取的平均数据; 通过比较存储器地址和温度边界码，将从存储器地址读取的数据或平均数据发送到第一存储体或第二存储体; 以及通过使用发送到第一存储体或第二存储体的数据来调整电容器阵列与对应于当前温度的电容。

公开(公告)号：US20090154564A1

公开(公告)日：2009-06-18

申请号：US12191733

申请日：2008-08-14

Applicant: Jin Ho HAN ,  Suk Ho Lee ,  Seong Mo Park ,  Nak Woong Eum

Inventor： Jin Ho HAN ,  Suk Ho Lee ,  Seong Mo Park ,  Nak Woong Eum

IPC: H04N7/26

CPC classification number: H04N19/523 ,  H04N19/43

Abstract: Provided is a motion estimation apparatus for moving picture coding. The apparatus includes a 1-pel buffer for storing 1-pel unit pixels using luminance signals of a reference frame which correspond to macroblocks of a current frame, a 1-pel estimator for calculating 1-pel unit motion vectors and minimum costs in correspondence to the macroblocks of the current frame and the pixels stored in the 1-pel buffer, a ½-pel interpolator for performing ½-pel unit interpolation using the pixels stored in the 1-pel buffer, a ½-pel buffer for storing the ½-pel unit interpolated pixels, a ½-pel estimator for calculating ½-pel unit motion vectors and minimum costs in correspondence to the pixels stored in the ½-pel buffer, the values calculated by the 1-pel estimator, and the macroblocks of the current frame, a ¼-pel interpolator for performing ¼-pel unit interpolation using the pixels stored in the ½-pel and 1-pel buffers, a ¼-pel buffer for storing the ¼-pel unit interpolated pixels, and a ¼-pel estimator for calculating ¼-pel unit motion vectors and minimum costs in correspondence to the pixels stored in the ¼-pel buffer, the values calculated by the ½-pel estimator, and the macroblocks of the current frame.

Abstract translation: 提供了一种用于运动图像编码的运动估计装置。 该装置包括：1个像素缓冲器，用于使用与当前帧的宏块相对应的参考帧的亮度信号来存储1个像素单位像素; 1像素估计器，用于计算1像素单位运动矢量，并对应于最小成本 当前帧的宏块和存储在1-像素缓冲器中的像素，1/2像素内插器，用于使用存储在1-像素缓冲器中的像素进行1/2像素单位内插;½像素缓冲器，用于存储1/2像素缓冲器， 像素单位内插像素，用于计算1/2像素单位运动矢量的1/2像素估计器和对应于存储在1/2像素缓冲器中的像素的最小成本，由1-像素估计器计算的值和当前的宏块 帧，¼贝尔内插器，用于使用存储在1/2贝尔和1贝尔缓冲器中的像素执行1/4贝尔单位内插，用于存储1/4贝尔单位内插像素的1/4贝尔缓冲器，以及1/4贝尔估计器 用于计算¼像素单位运动矢量 对应于存储在1/4贝尔缓冲器中的像素的最小成本，由1/2贝尔估计器计算的值和当前帧的宏块。

公开(公告)号：US20070162645A1

公开(公告)日：2007-07-12

申请号：US11524069

申请日：2006-09-20

Applicant: Jin Ho Han ,  Han Jin Cho

Inventor： Jin Ho Han ,  Han Jin Cho

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: Provided is a communication system for improving utilization of on-chip communication architecture and eliminating waiting of a master to use a bus. The communication system includes: a direct memory access controller handling high-capacity data communication among a memory and peripheral devices; a communication switch connected with the direct memory access controller, transferring a header storing information on a location of a passive circuit and a continuous transfer size, and an initial address from an active circuit to the passive circuit, and sending and receiving data to/from the direct memory access controller; and a memory controller sending and receiving the data and the address to/from the direct memory access controller. According to the communication system, a request of an active circuit is not delayed between on-chip circuits, several active circuits can simultaneously transfer data, data communication rate between passive circuits increases, and communication congestion between the passive circuits can be controlled.

Abstract translation: 提供了一种用于提高片上通信体系结构的利用并消除主机等待使用总线的通信系统。 通信系统包括：直接存储器访问控制器，用于处理存储器和外围设备之间的高容量数据通信; 与直接存储器存取控制器连接的通信开关，将存储有关无源电路的位置的信息和连续的传送大小的报头以及从有源电路的初始地址传送到无源电路，以及发送和接收数据到/从 直接存储器存取控制器; 以及存储器控制器向/从直接存储器存取控制器发送和接收数据和地址。 根据通信系统，有源电路的请求在片上电路之间不被延迟，几个有源电路可以同时传输数据，无源电路之间的数据通信速率增加，并且可以控制无源电路之间的通信拥塞。

公开(公告)号：US08904199B2

公开(公告)日：2014-12-02

申请号：US13207484

申请日：2011-08-11

Applicant: Jin Ho Han

Inventor： Jin Ho Han

IPC: G06F1/00 ,  G06F1/32 ,  G06F1/26

CPC classification number: G06F1/324 ,  G06F1/26 ,  Y02D10/126

Abstract: The present invention relates to an apparatus for controlling power of mufti core processor, which includes a power control device by core unit, controls a plurality of power-related parameters by core unit, and thus decreases a load for power management and enables realization of a low power multi core processor through minute power control. The apparatus includes a processor core adapted to provide code information on an application program for executing to a power regulation controller, and a power regulation controller adapted to receive the code information on the application program from the processor core to determine an operation frequency of the processor core, set an operation voltage, a clock-gating value and a power-gating value according to the determined operation frequency, and provide the set values and voltage to the processor core.

Abstract translation: 本发明涉及一种用于控制核心处理器的功率的装置，其包括核心单元的功率控制装置，通过核心单元控制多个与功率有关的参数，从而减少用于电力管理的负载，并且能够实现 低功耗多核处理器，通过微功率控制。 所述设备包括处理器核心，其适于提供关于用于执行功率调节控制器的应用程序的代码信息;以及功率调节控制器，其适于从所述处理器核心接收关于所述应用程序的代码信息，以确定所述处理器的操作频率 根据所确定的工作频率设置工作电压，时钟门控值和电源门控值，并将设定值和电压提供给处理器核心。

公开(公告)号：US20100156404A1

公开(公告)日：2010-06-24

申请号：US11909293

申请日：2006-03-24

Applicant: Jin Ho HAN ,  Dong Hyun KIM ,  In Seong SONG

Inventor： Jin Ho HAN ,  Dong Hyun KIM ,  In Seong SONG

IPC: G01R33/06 ,  G01N29/04

CPC classification number: A61B8/12 ,  A61B8/4461

Abstract: The present invention relates to an ultrasonic probe for producing a real-time three dimensional live action image (a four dimensional image), which has a long lifetime, and an improved image quality, can prevent malfunction. The ultrasonic probe for producing a four dimensional image includes power transmission means for transmission of power from an upright motor to a module (2) having acoustic elements for swinging the module, the power transmission means includes a first link (20) having a horizontal portion (22) directly connected to a motor shaft, and a sloped portion projected upward from one side end of the horizontal portion at an angle in conformity with a locus of a swing action of the module, and a second link (21) comprising a horizontal (29) having an interlocking connected thereto and a pair of parallel portion (30) and (31) projected upwardly from opposite ends of the horizontal portion, such that the second link is interlocked along the first link in a state of being interposed between the first link and the module, wherein the interlocking shaft (28) is connected with an inclined portion of the first link by a shaft and the pair of parallel portions is mounting to a lower side of the module in a horizontal direction with a shaft.

Abstract translation: 本发明涉及一种用于制造具有长寿命和改进的图像质量的实时三维实况动作图像（四维图像）的超声波探头，可以防止故障。 用于产生四维图像的超声波探头包括用于将功率从直立马达传输到具有用于摆动模块的声学元件的模块（2）的动力传递装置，动力传递装置包括具有水平部分的第一连杆 （22），以及从所述水平部的一侧端部向与所述模块的摆动动作的轨迹一致的角度向上突出的倾斜部，以及包括水平方向的第二连杆（21） （29）和从所述水平部分的相对端部向上突出的一对平行部分（30）和（31），使得所述第二连杆沿着所述第一连杆以处于所述水平部分之间的状态互锁 第一连杆和模块，其中联锁轴（28）通过轴与第一连杆的倾斜部分连接，并且该对平行部分安装到模块的下侧 e在水平方向与轴。

公开(公告)号：US20110135008A1

公开(公告)日：2011-06-09

申请号：US12961196

申请日：2010-12-06

Applicant: Jin Ho HAN ,  Kyoung Seon Shin

Inventor： Jin Ho HAN ,  Kyoung Seon Shin

IPC: H04N7/30

CPC classification number: H04N19/57 ,  H04N19/433

Abstract: A video processing system includes a frame memory, an input video buffer, a macroblock buffer, a first search window buffer, a second search window buffer, a deblocked macroblock buffer, and a frame memory controller. The frame memory stores frame data. The input video buffer stores input data and transfers the input data to the frame memory. The macroblock buffer stores a plurality of macroblocks. The first search window buffer stores a search region of a reference frame for coarse motion estimation. The second search window buffer stores a search region of a reference frame for fine motion estimation. The deblocked macroblock buffer stores the performance results of a deblocking filter. The frame memory controller performs write/read operations on the input video buffer, the macroblock buffer, the first search window buffer, the second search window buffer, the deblocked macroblock buffer and the frame memory.

Abstract translation: 视频处理系统包括帧存储器，输入视频缓冲器，宏块缓冲器，第一搜索窗缓冲器，第二搜索窗缓冲器，解块宏块缓冲器和帧存储器控制器。 帧存储器存储帧数据。 输入视频缓冲器存储输入数据并将输入数据传送到帧存储器。 宏块缓冲器存储多个宏块。 第一搜索窗口缓冲器存储用于粗略运动估计的参考帧的搜索区域。 第二搜索窗缓冲器存储用于精细运动估计的参考帧的搜索区域。 去块宏块缓冲器存储解块滤波器的性能结果。 帧存储器控制器对输入视频缓冲器，宏块缓冲器，第一搜索窗缓冲器，第二搜索窗缓冲器，解块宏块缓冲器和帧存储器执行写/读操作。