公开(公告)号：US07919373B2

公开(公告)日：2011-04-05

申请号：US12165182

申请日：2008-06-30

Applicant: Jin-Ku Lee ,  Jae-Geun Oh ,  Sun-Hwan Hwang

Inventor： Jin-Ku Lee ,  Jae-Geun Oh ,  Sun-Hwan Hwang

IPC: H01L21/336 ,  H01L21/00 ,  H01L21/20

CPC classification number: H01L21/02667 ,  H01L21/02532 ,  H01L21/02675 ,  H01L27/10876 ,  H01L27/10894

Abstract: A method for doping polysilicon improves a doping profile during plasma doping and includes forming a silicon layer using two separate operations. After forming a first silicon layer, thermal annealing is performed to crystallize the first silicon layer, such that the uniformity of a doping concentration according to the depth of a layer inside is improved during plasma doping. Additionally, a doping concentration at the interface between a polysilicon layer and a gate oxide layer is increased. A by-product deposition layer is reduced, which is formed on the surface of a polysilicon layer due to the increase of a doping concentration in a polysilicon layer. As a result, the dopant loss, which is caused by the removing and cleansing of an ion implantation barrier used during doping, is reduced.

Abstract translation: 掺杂多晶硅的方法改善了等离子体掺杂期间的掺杂分布，并且包括使用两个单独的操作形成硅层。 在形成第一硅层之后，进行热退火以使第一硅层结晶，使得在等离子体掺杂期间根据内层的深度的掺杂浓度的均匀性得到改善。 此外，在多晶硅层和栅极氧化物层之间的界面处的掺杂浓度增加。 由于多晶硅层中的掺杂浓度的增加，副产物沉积层被还原，其形成在多晶硅层的表面上。 结果，减少了在掺杂期间使用的离子注入阻挡层的去除和清洁引起的掺杂剂损耗。

公开(公告)号：US20100084720A1

公开(公告)日：2010-04-08

申请号：US12318503

申请日：2008-12-30

Applicant: Jae-Geun Oh ,  Jin-Ku Lee ,  Min-Ae Ju

Inventor： Jae-Geun Oh ,  Jin-Ku Lee ,  Min-Ae Ju

IPC: H01L29/78 ,  H01L21/425

CPC classification number: H01L29/4916 ,  H01L21/265 ,  H01L21/28035 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/66621

Abstract: A gate of a semiconductor device includes a substrate, and a polysilicon layer over the substrate, wherein the polysilicon layer is doped with first conductive type impurities having a concentration that decreases when receding from the substrate and counter-doped with second conductive type impurities having a concentration that increases when receding from the substrate.

Abstract translation: 半导体器件的栅极包括衬底和衬底上的多晶硅层，其中多晶硅层掺杂有从衬底退出时具有降低的浓度的第一导电型杂质，并与第二导电类型杂质反相掺杂， 从底物后退时增加的浓度。

公开(公告)号：US08354342B2

公开(公告)日：2013-01-15

申请号：US12939677

申请日：2010-11-04

Applicant: Jae-Geun Oh ,  Seung-Joon Jeon ,  Jin-Ku Lee ,  Mi-Ri Lee ,  Bong-Seok Jeon

Inventor： Jae-Geun Oh ,  Seung-Joon Jeon ,  Jin-Ku Lee ,  Mi-Ri Lee ,  Bong-Seok Jeon

IPC: H01L23/522

CPC classification number: H01L29/7813 ,  H01L21/743 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method for fabricating a semiconductor device includes forming a plurality of bodies that are each isolated from another by a trench and each include a diffusion barrier region with a sidewall exposed to the trench, forming a doped layer gap-filling the trench, forming a sidewall junction at the exposed sidewall of the diffusion barrier region by annealing the doped layer, and forming a conductive line coupled with the sidewall junction to fill the trench.

Abstract translation: 一种制造半导体器件的方法包括：形成多个通过沟槽与另一个隔离的主体，并且每个都包括具有暴露于沟槽的侧壁的扩散阻挡区域，形成填充沟槽的掺杂层间隙，形成侧壁 通过退火掺杂层而在扩散阻挡区域的暴露的侧壁处形成连接，并且形成与侧壁接合部连接以填充沟槽的导电线。

公开(公告)号：US08063453B2

公开(公告)日：2011-11-22

申请号：US12318503

申请日：2008-12-30

Applicant: Jae-Geun Oh ,  Jin-Ku Lee ,  Min-Ae Ju

Inventor： Jae-Geun Oh ,  Jin-Ku Lee ,  Min-Ae Ju

IPC: H01L29/78 ,  H01L21/425

CPC classification number: H01L29/4916 ,  H01L21/265 ,  H01L21/28035 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/66621

Abstract: A gate of a semiconductor device includes a substrate, and a polysilicon layer over the substrate, wherein the polysilicon layer is doped with first conductive type impurities having a concentration that decreases when receding from the substrate and counter-doped with second conductive type impurities having a concentration that increases when receding from the substrate.

Abstract translation: 半导体器件的栅极包括衬底和衬底上的多晶硅层，其中多晶硅层掺杂有从衬底退出时具有降低的浓度的第一导电型杂质，并与第二导电类型杂质反相掺杂， 从底物后退时增加的浓度。

公开(公告)号：US20110073940A1

公开(公告)日：2011-03-31

申请号：US12649999

申请日：2009-12-30

Applicant: Jin-Ku LEE ,  Young-Ho Lee ,  Mi-Ri Lee

Inventor： Jin-Ku LEE ,  Young-Ho Lee ,  Mi-Ri Lee

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7845 ,  H01L21/28518 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7856

Abstract: A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second conductive layer over the first conductive layer, forming a plurality of active regions by etching the second conductive layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench.

Abstract translation: 一种制造半导体器件的方法包括：在半导体衬底上形成掺杂有用于形成电池结的杂质的第一导电层，在第一导电层上形成第二导电层，通过蚀刻第二导电层形成多个有源区 和所述第一导电层，所述多个有源区域通过沟槽彼此分开，形成连接到所述第一导电层的侧壁的侧面接触，以及形成多个金属位线，每个金属位线连接到所述侧面接触和填充 每个沟槽的一部分。

公开(公告)号：US07888245B2

公开(公告)日：2011-02-15

申请号：US11743670

申请日：2007-05-03

Applicant: Jae-Sung Roh ,  Jae-Geun Oh ,  Hyun-Chul Sohn ,  Sun-Hwan Hwang ,  Jin-Ku Lee

Inventor： Jae-Sung Roh ,  Jae-Geun Oh ,  Hyun-Chul Sohn ,  Sun-Hwan Hwang ,  Jin-Ku Lee

IPC: H01L21/20

CPC classification number: H01L21/2236 ,  H01L21/28035

Abstract: A plasma doping method includes providing a doping source over a substrate. The doping source includes dopants that are to be injected into the substrate. At least two different bias voltages are applied to inject the dopants from the doping source to the substrate.

Abstract translation: 等离子体掺杂方法包括在衬底上提供掺杂源。 掺杂源包括要注入衬底的掺杂剂。 施加至少两个不同的偏置电压以将掺杂剂从掺杂源注入衬底。

公开(公告)号：US4057167A

公开(公告)日：1977-11-08

申请号：US746604

申请日：1976-12-01

Applicant: Jin Ku Lee

Inventor： Jin Ku Lee

IPC: B65D47/28 ,  A47G19/22 ,  B65D43/20 ,  B65D51/18

CPC classification number: B65D47/286

Abstract: A valved closure for a disposable drinking receptacle containing a consumable beverage is disclosed. The valved receptacle closure comprises a thin plastic cover having a peripheral groove adapted to sealingly engage with the rim of a drinking receptacle and a drinking opening therein through which the beverage is consumed. A slide valve is received in a recess formed in the cover and is movable into a closed position over the drinking opening. A releasable latch mechanism cooperates with the valve to secure the valve in its closed position against the force of a resilient member, such as a spring. When the latch is released, the resilient member urges the valve into its open position exposing the drinking opening to permit drinking therefrom.

Abstract translation: 公开了一种用于含有可消费饮料的一次性饮用容器的阀盖。 带阀的容器封闭件包括薄塑料盖，其具有适于与饮用容器的边缘密封接合的周边凹槽和其中饮料被消耗的饮用开口。 滑阀被容纳在形成在盖中的凹部中并且可移动到饮用开口上方的关闭位置。 可释放的闩锁机构与阀配合，以克服弹性构件（例如弹簧）的力将阀固定在其关闭位置。 当闩锁被释放时，弹性构件促使阀进入其暴露饮用开口以允许从其中饮用的打开位置。