Micro-fluid ejector pattern for improved performance
    11.
    发明授权
    Micro-fluid ejector pattern for improved performance 有权
    微流体喷射器模式,以提高性能

    公开(公告)号:US07850286B2

    公开(公告)日:2010-12-14

    申请号:US11767568

    申请日:2007-06-25

    IPC分类号: B41J2/05

    CPC分类号: B41J2/1404

    摘要: A micro-fluid ejection head and method for reducing a stagger pattern distance and improving droplet placement, on a receiving medium. The micro-fluid ejection head includes a substrate containing a plurality of ejection actuators on a device surface thereof and a fluid supply slot for providing fluid to be ejected by the micro-fluid ejection head. The ejection head also includes a flow feature component in flow communication with the fluid supply slot and configured for providing fluid ejection chambers and fluid supply channels for the fluid ejection chambers. Adjacent first and second ejection actuators in a substantially linear array of ejection actuators are each spaced a first distance from the fluid supply slot and second and third ejection actuators in the linear array of ejection actuators are each spaced a second distance from the fluid supply slot that is less than the first distance.

    摘要翻译: 一种用于在接收介质上减少交错图案距离并改善液滴布置的微流体喷射头和方法。 微流体喷射头包括在其装置表面上包含多个喷射致动器的基板和用于提供由微流体喷射头喷射的流体的流体供应槽。 喷射头还包括与流体供应槽流体连通的流动特征部件,并且构造成用于为流体喷射室提供流体喷射室和流体供应通道。 相邻的第一和第二喷射致动器以大致线性排列的排出致动器阵列分别与液体供应槽隔开第一距离,并且排出致动器的线性阵列中的第二和第三排出致动器与流体供应槽间隔开第二距离, 小于第一距离。

    MICRO-FLUID EJECTOR PATTERN FOR IMPROVED PERFORMANCE
    12.
    发明申请
    MICRO-FLUID EJECTOR PATTERN FOR IMPROVED PERFORMANCE 有权
    用于改进性能的微流体喷射器模式

    公开(公告)号:US20080316277A1

    公开(公告)日:2008-12-25

    申请号:US11767568

    申请日:2007-06-25

    IPC分类号: B41J2/05

    CPC分类号: B41J2/1404

    摘要: A micro-fluid ejection head and method for reducing a stagger pattern distance and improving droplet placement, on a receiving medium. The micro-fluid ejection head includes a substrate containing a plurality of ejection actuators on a device surface thereof and a fluid supply slot for providing fluid to be ejected by the micro-fluid ejection head. The ejection head also includes a flow feature component in flow communication with the fluid supply slot and configured for providing fluid ejection chambers and fluid supply channels for the fluid ejection chambers. Adjacent first and second ejection actuators in a substantially linear array of ejection actuators are each spaced a first distance from the fluid supply slot and second and third ejection actuators in the linear array of ejection actuators are each spaced a second distance from the fluid supply slot that is less than the first distance.

    摘要翻译: 一种用于在接收介质上减少交错图案距离并改善液滴布置的微流体喷射头和方法。 微流体喷射头包括在其装置表面上包含多个喷射致动器的基板和用于提供由微流体喷射头喷射的流体的流体供应槽。 喷射头还包括与流体供应槽流体连通的流动特征部件,并且构造成用于为流体喷射室提供流体喷射室和流体供应通道。 相邻的第一和第二喷射致动器以大致线性排列的排出致动器阵列分别与液体供应槽隔开第一距离,并且排出致动器的线性阵列中的第二和第三排出致动器与流体供应槽间隔开第二距离, 小于第一距离。

    Distributed programmed memory cell overwrite protection
    13.
    发明授权
    Distributed programmed memory cell overwrite protection 有权
    分布式编程存储单元覆盖保护

    公开(公告)号:US07310282B2

    公开(公告)日:2007-12-18

    申请号:US11322417

    申请日:2005-12-30

    IPC分类号: G11C17/18

    CPC分类号: G11C17/16 G11C17/18

    摘要: A method and circuit for preventing the overprogramming of a memory cell. A fuse circuit is operable to be blown. A combinational logic circuit receives a signal from the fuse circuit, indicating whether or not the fuse has been blown, and controls the programming of the memory cell. The programming of the memory cell is prevented if the fuse circuit has been blown.

    摘要翻译: 一种用于防止存储器单元过度编程的方法和电路。 保险丝电路可操作地被吹制。 组合逻辑电路接收来自保险丝电路的信号,指示保险丝是否已被熔断,并控制存储器单元的编程。 如果保险丝电路已经被烧断,则防止存储器单元的编程。

    Methods and Apparatuses for Trimming Circuits
    14.
    发明申请
    Methods and Apparatuses for Trimming Circuits 审中-公开
    修剪电路的方法和设备

    公开(公告)号:US20070285105A1

    公开(公告)日:2007-12-13

    申请号:US11421820

    申请日:2006-06-02

    IPC分类号: G01R31/04

    CPC分类号: G01D18/008

    摘要: The inventions relate to methods for trimming integrated circuits. Various embodiments include providing a method to trim an integrated circuit wherein trim data is stored in an on-board memory and then sent off of the circuit to be operated on by an external device. Corresponding trim data is then sent back to the integrated circuit in order to potentially modify the function of one or more analog devices along the circuit. Other embodiments include methods for trimming integrated circuits wherein trim data is stored in an on-board memory and retrieved using an on-board sequencer. The retrieved data is used to modify a function of one or more analog devices on the integrated circuit.

    摘要翻译: 本发明涉及用于修整集成电路的方法。 各种实施例包括提供一种修整集成电路的方法,其中修剪数据存储在板上存储器中,然后从电路发送以由外部设备操作。 相应的修剪数据然后被发送回集成电路,以便潜在地修改沿着电路的一个或多个模拟设备的功能。 其他实施例包括用于修整集成电路的方法,其中修剪数据被存储在板载存储器中并使用板载定序器进行检索。 检索的数据用于修改集成电路上的一个或多个模拟设备的功能。

    Inkjet printer having improved ejector chip
    15.
    发明授权
    Inkjet printer having improved ejector chip 有权
    具有改进的喷射器芯片的喷墨打印机

    公开(公告)号:US06890066B2

    公开(公告)日:2005-05-10

    申请号:US10443477

    申请日:2003-05-22

    IPC分类号: B41J2/05 B41J2/14

    摘要: An inkjet printer includes a printhead for ejecting ink onto a print medium. The printhead includes electrical and mechanical structure for controlling the ejection of the ink. The printhead includes an ink ejector chip having at least one active device, such as a transistor and the like. A guard ring substantially surrounds select active devices included on the chip. The guard ring tends to prevent latch-up when the chip operates to energize the ink. The chip is manufactured using a substrate devoid of an overlying epitaxial layer which tends to reduce the cost of manufacturing the chip.

    摘要翻译: 喷墨打印机包括用于将墨喷射到打印介质上的打印头。 打印头包括用于控制油墨喷射的电气和机械结构。 打印头包括具有至少一个有源器件(诸如晶体管等)的墨水排出器芯片。 保护环基本上包围芯片上包括的选择有源器件。 当芯片操作以使墨水通电时,保护环趋向于防止闩锁。 该芯片使用没有上覆外延层的衬底制造,这倾向于降低制造芯片的成本。

    Enhanced communications protocol for improved modularity in a micro-fluid ejection device
    16.
    发明授权
    Enhanced communications protocol for improved modularity in a micro-fluid ejection device 有权
    增强的通信协议,用于改善微流体喷射装置中的模块化

    公开(公告)号:US07992952B2

    公开(公告)日:2011-08-09

    申请号:US11760961

    申请日:2007-06-11

    IPC分类号: B41J29/38

    CPC分类号: G06K15/102

    摘要: Methods and apparatus for improving modularity in a micro-fluid ejection device and for providing instruction data to a plurality of data handling devices within a micro-fluid ejection device. The method includes generating device data and appending an address to the device data to generate instruction data. The address typically indicates at least one data handling device within the micro-fluid ejection device for which the device data is intended. The instruction data is provided to a plurality of data handling devices including at least one data controller. The data controller is operated to decode the address from the instruction data and select at least one data handling device to receive the device data based upon the decoded address. The device data is thereby input into each selected data handling device and subsequently used to operate the micro-fluid ejection device.

    摘要翻译: 用于改进微流体喷射装置中的模块化并用于向微流体喷射装置内的多个数据处理装置提供指令数据的方法和装置。 该方法包括产生设备数据并将地址附加到设备数据以产生指令数据。 该地址通常表示微流体喷射装置内的至少一个数据处理装置,用于该装置数据的数据处理装置。 指令数据被提供给包括至少一个数据控制器的多个数据处理装置。 数据控制器被操作以从指令数据解码地址,并且选择至少一个数据处理设备以基于解码的地址接收设备数据。 因此,装置数据被输入到每个所选择的数据处理装置中,随后用于操作微流体喷射装置。

    Ink jet heater chip with internally generated clock signal
    17.
    发明授权
    Ink jet heater chip with internally generated clock signal 有权
    喷墨加热器芯片具有内部产生的时钟信号

    公开(公告)号:US07452041B2

    公开(公告)日:2008-11-18

    申请号:US10636928

    申请日:2003-08-07

    IPC分类号: B41J29/38

    摘要: A method for generating a clock pulse train within a heater chip of an ink jet printer that is used to serially load data into the chip eliminates the need for an externally generated clock signal. These heater chips with internally generated clock signals allow for reduced print head cost.

    摘要翻译: 用于在用于将数据串行加载到芯片中的喷墨打印机的加热器芯片内产生时钟脉冲串的方法消除了对外部产生的时钟信号的需要。 这些具有内部产生的时钟信号的加热器芯片允许降低打印头成本。

    Reduced size inkjet printhead heater chip having integral voltage regulator and regulating capacitors
    18.
    发明授权
    Reduced size inkjet printhead heater chip having integral voltage regulator and regulating capacitors 有权
    具有集成稳压器和调节电容器的缩小尺寸喷墨打印头加热器芯片

    公开(公告)号:US06789871B2

    公开(公告)日:2004-09-14

    申请号:US10331001

    申请日:2002-12-27

    IPC分类号: B41J29393

    摘要: An inkjet printhead heater chip has an integral voltage regulator that derives two output voltages from a single chip input voltage. One of the two output voltages powers control logic circuitry as the other powers FET drivers. Preferred output voltages include +3.3 volts for the control logic circuitry and +7.5 volts for the FET drivers. A Vgs of the FET is about +7.5 volts which enables a FET area width of about 400 microns. Outputs of the control logic circuitry provide input to the FET drivers. A resistive heater for ejecting ink couples between a drain of the FET and the chip input voltage. Voltage regulating capacitors exist on the heater chip in parallel with the input voltage and each of the output voltages. Preferred capacitors have a gate oxide and a polysilicon layer overlying a substrate. Inkjet printers for housing the printheads are also disclosed.

    摘要翻译: 喷墨打印头加热器芯片具有从单个芯片输入电压导出两个输出电压的积分电压调节器。 两个输出电压之一为另一个供电FET驱动器供电控制逻辑电路。 优选的输出电压包括控制逻辑电路的+3.3伏特,FET驱动器的+7.5伏特。 FET的Vgs约为+7.5伏,这使得FET面积宽度约为400微米。 控制逻辑电路的输出为FET驱动器提供输入。 一种用于在FET的漏极和芯片输入电压之间喷射墨水耦合的电阻加热器。 电压调节电容器与输入电压和每个输出电压并联,存在于加热器芯片上。 优选的电容器具有覆盖在衬底上的栅极氧化物和多晶硅层。 还公开了用于容纳打印头的喷墨打印机。

    Latching serial data in an ink jet print head

    公开(公告)号:US06547356B2

    公开(公告)日:2003-04-15

    申请号:US09780555

    申请日:2001-02-09

    IPC分类号: B41J2938

    摘要: A print data loading circuit receives N bits of serial data on a serial input data line, and provides the input data to a data bus in an addressing circuit for addressing one or more image-forming elements in a printing device. The data loading circuit includes an N-bit serial shift register having N number of serially-coupled single-bit storage registers. The data loading circuit also includes N−1 number of data latches, each having a data input coupled to a data output of a corresponding one of the single-bit storage registers. The data outputs of the data latches are coupled to N−1 number of selection lines that are coupled to the data bus. Each data latch has a clock input that is coupled to the data output of the Nth storage register. Based on this configuration, a bit provided at the Nth-register data output acts as a load trigger bit to cause the other data bits in the other single-bit storage registers to be loaded into the N−1 number of data latches. By providing the trigger bit from the Nth register of the shift register, the present invention eliminates the need for a second clock input to latch the print data into the data latches. Eliminating a second clock input reduces print head costs and potential EMI problems.