公开(公告)号：US20130272059A1

公开(公告)日：2013-10-17

申请号：US13446250

申请日：2012-04-13

Applicant: Kai-Chun LIN ,  Hung-Chang YU ,  Yue-Der CHIH ,  Chun-Jung LIN

Inventor： Kai-Chun LIN ,  Hung-Chang YU ,  Yue-Der CHIH ,  Chun-Jung LIN

IPC: G11C11/16

CPC classification number: G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C29/74

Abstract: A magnetoresistive memory has first and second magnetic tunnel junction (MTJ) elements operated differentially, each with a pinned magnetic layer and a free magnetic layer that can have field alignments that are parallel or anti-parallel, producing differential high and low resistance states representing a bit cell value. Writing a high resistance state to an element requires an opposite write current polarity through the pinned and free layers, and differential operation requires that the two MTJ elements be written to different resistance states. One aspect is to arrange or connect the layers in normal and reverse order relative to a current bias source, thereby achieving opposite write current polarities relative to the layers using the same current polarity relative to the current bias source. The differentially operated MTJ elements can supplement or replace single MTJ elements in a nonvolatile memory bit cell array.

Abstract translation: 磁阻存储器具有差分地操作的第一和第二磁性隧道结（MTJ）元件，每个具有钉扎磁性层和可以具有并联或反平行的场对准的自由磁性层，产生表示 位单元格值。 向元件写入高电阻状态需要通过固定和自由层的相反的写入电流极性，并且差分操作要求将两个MTJ元件写入不同的电阻状态。 一个方面是相对于电流偏置源以正常和相反的顺序布置或连接层，从而相对于使用相对于电流偏置源的相同电流极性的层获得相反的写入电流极性。 差分操作的MTJ元件可以补充或替代非易失性存储器位单元阵列中的单个MTJ元件。

公开(公告)号：US20130265820A1

公开(公告)日：2013-10-10

申请号：US13443056

申请日：2012-04-10

Applicant: Yue-Der CHIH ,  Chin- Yi HUANG ,  Chun-Jung LIN ,  Kai-Chun LIN ,  Hung-Chang YU

Inventor： Yue-Der CHIH ,  Chin- Yi HUANG ,  Chun-Jung LIN ,  Kai-Chun LIN ,  Hung-Chang YU

IPC: G11C11/16

CPC classification number: G11C11/16 ,  G11C11/15 ,  G11C11/1673

Abstract: Magneto-resistive memory bit cells in an array have high or low resistance states storing logic values. During read operations, a bias source is coupled to an addressed memory word, coupling a parameter related to cell resistance to a sense amplifier at each bit position. The sense amplifiers determine whether the parameter value is greater or less than a reference value between the high and low resistance states. The reference value is derived by averaging or splitting a difference of resistances of reference cells at high and/or low resistance states. Bias current is conducted over address lines with varying resistance, due to different distances between the sense amplifiers and addressed memory words, which is canceled by inserting into the comparison circuit a resistance from a dummy addressing array, equal to the resistance of the conductor addressing the selected word line and bit position.

Abstract translation: 阵列中的磁阻存储器位单元具有存储逻辑值的高或低电阻状态。 在读取操作期间，偏置源耦合到寻址的存储器字，将与单元电阻相关的参数耦合到每个位位置的读出放大器。 读出放大器确定参数值是大于还是小于高电阻状态和低电阻状态之间的参考值。 参考值是通过在高和/或低电阻状态下对参考电池的电阻差进行平均或分割得出的。 由于感测放大器和寻址的存储器字之间的距离不同，偏置电流在具有变化的电阻的地址线上进行，这通过将来自虚拟寻址阵列的电阻插入到比较电路中来抵消，等于导体寻址的电阻 选择的字线和位位置。

公开(公告)号：US20130188418A1

公开(公告)日：2013-07-25

申请号：US13356920

申请日：2012-01-24

Applicant: Tien-Wei CHIANG ,  Kai-Chun LIN ,  Ya-Chen KAO ,  Hung-Chang YU

Inventor： Tien-Wei CHIANG ,  Kai-Chun LIN ,  Ya-Chen KAO ,  Hung-Chang YU

IPC: G11C11/16 ,  H01L29/82

CPC classification number: H01L27/222 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  H01L43/08

Abstract: A magnetoresistive random access memory (MRAM) cell includes a magnetic tunnel junction (MTJ), a top electrode disposed over the MTJ, a bottom electrode disposed below the MTJ, and an induction line disposed above or below the MTJ. The induction line is configured to induce a magnetic field at the MTJ.

Abstract translation: 磁阻随机存取存储器（MRAM）单元包括磁性隧道结（MTJ），设置在MTJ上方的顶部电极，设置在MTJ下方的底部电极以及设置在MTJ上方或下方的感应线。 感应线被配置为在MTJ处诱导磁场。

公开(公告)号：US20170174855A1

公开(公告)日：2017-06-22

申请号：US15096289

申请日：2016-04-12

Applicant: Erika Yang ,  Kai Chun Lin

Inventor： Erika Yang ,  Kai Chun Lin

IPC: C08J7/12 ,  B05D1/00 ,  H01J37/32

CPC classification number: H01J37/32009 ,  B05D1/005 ,  B05D5/08 ,  C03C17/38 ,  C03C17/42 ,  C03C2217/76 ,  H01J37/3244 ,  H01J2237/334

Abstract: The embodiments disclose a method of using a molecular self-assembly of a predetermined spherical or cylindrical block copolymer (BCP) to create a nano-scale dot array pattern, transferring the BCP pattern into a chromium (Cr) hard mask layer, and then into a substrate. The patterned substrate is chemically modified with a predetermined self-assembled monolayer (SAM) with a hydrophobic functional group to form a super-hydrophobic surface.

公开(公告)号：US08964458B2

公开(公告)日：2015-02-24

申请号：US13446250

申请日：2012-04-13

Applicant: Kai-Chun Lin ,  Hung-Chang Yu ,  Yue-Der Chih ,  Chun-Jung Lin

Inventor： Kai-Chun Lin ,  Hung-Chang Yu ,  Yue-Der Chih ,  Chun-Jung Lin

IPC: G11C11/16

CPC classification number: G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C29/74

Abstract: A magnetoresistive memory has first and second magnetic tunnel junction (MTJ) elements operated differentially, each with a pinned magnetic layer and a free magnetic layer that can have field alignments that are parallel or anti-parallel, producing differential high and low resistance states representing a bit cell value. Writing a high resistance state to an element requires an opposite write current polarity through the pinned and free layers, and differential operation requires that the two MTJ elements be written to different resistance states. One aspect is to arrange or connect the layers in normal and reverse order relative to a current bias source, thereby achieving opposite write current polarities relative to the layers using the same current polarity relative to the current bias source. The differentially operated MTJ elements can supplement or replace single MTJ elements in a nonvolatile memory bit cell array.

Abstract translation: 磁阻存储器具有差分地操作的第一和第二磁性隧道结（MTJ）元件，每个具有钉扎磁性层和可以具有并联或反平行的场对准的自由磁性层，产生表示 位单元格值。 向元件写入高电阻状态需要通过固定和自由层的相反的写入电流极性，并且差分操作要求将两个MTJ元件写入不同的电阻状态。 一个方面是相对于电流偏置源以正常和相反的顺序布置或连接层，从而相对于使用相对于电流偏置源的相同电流极性的层获得相反的写入电流极性。 差分操作的MTJ元件可以补充或替代非易失性存储器位单元阵列中的单个MTJ元件。

公开(公告)号：US08842489B2

公开(公告)日：2014-09-23

申请号：US13447318

申请日：2012-04-16

Applicant: Hung-Chang Yu ,  Ku-Feng Lin ,  Kai-Chun Lin ,  Yue-Der Chih

Inventor： Hung-Chang Yu ,  Ku-Feng Lin ,  Kai-Chun Lin ,  Yue-Der Chih

IPC: G11C5/14

CPC classification number: G11C11/418 ,  G11C8/08 ,  G11C11/4085

Abstract: A word line driver of a semiconductor memory includes logic circuitry for coupling a word line to a first node set at a first voltage level when the word line driver is in a first state or to a second node set at a second voltage level when the word line driver is in a second state. A capacitor is configured to be charged to a third voltage level that is greater than the first and second voltage levels. First and second transistors are configured to selectively couple the word line to the capacitor and to a third node set at a fourth voltage level when the word line driver is in a third state. The fourth voltage level is greater than the first voltage level and less than the second voltage level.

Abstract translation: 半导体存储器的字线驱动器包括逻辑电路，用于当字线驱动器处于第一状态时将字线耦合到设置在第一电压电平处的第一节点，或者当字线驱动器处于第二电压电平时将字线耦合到设置为第二电压电平的第二节点 线路驱动器处于第二状态。 电容器被配置为被充电到大于第一和第二电压电平的第三电压电平。 第一和第二晶体管被配置为当字线驱动器处于第三状态时，将字线选择性地耦合到电容器和设置在第四电压电平的第三节点。 第四电压电平大于第一电压电平并小于第二电压电平。

公开(公告)号：US20130242676A1

公开(公告)日：2013-09-19

申请号：US13447318

申请日：2012-04-16

Applicant: Hung-Chang YU ,  Ku-Feng LIN ,  Kai-Chun LIN ,  Yue-Der CHIH

Inventor： Hung-Chang YU ,  Ku-Feng LIN ,  Kai-Chun LIN ,  Yue-Der CHIH

IPC: G11C8/08 ,  G11C7/00

CPC classification number: G11C11/418 ,  G11C8/08 ,  G11C11/4085

Abstract: A word line driver of a semiconductor memory includes logic circuitry for coupling a word line to a first node set at a first voltage level when the word line driver is in a first state or to a second node set at a second voltage level when the word line driver is in a second state. A capacitor is configured to be charged to a third voltage level that is greater than the first and second voltage levels. First and second transistors are configured to selectively couple the word line to the capacitor and to a third node set at a fourth voltage level when the word line driver is in a third state. The fourth voltage level is greater than the first voltage level and less than the second voltage level.

Abstract translation: 半导体存储器的字线驱动器包括逻辑电路，用于当字线驱动器处于第一状态时将字线耦合到设置在第一电压电平处的第一节点，或者当字线驱动器处于第二电压电平时将字线耦合到设置为第二电压电平的第二节点 线路驱动器处于第二状态。 电容器被配置为被充电到大于第一和第二电压电平的第三电压电平。 第一和第二晶体管被配置为当字线驱动器处于第三状态时，将字线选择性地耦合到电容器和设置在第四电压电平的第三节点。 第四电压电平大于第一电压电平并小于第二电压电平。

公开(公告)号：US20130201754A1

公开(公告)日：2013-08-08

申请号：US13364756

申请日：2012-02-02

Applicant: Hung-Chang Yu ,  Kai-Chun Lin ,  Yue-Der Chih ,  Chun-Jung Lin

Inventor： Hung-Chang Yu ,  Kai-Chun Lin ,  Yue-Der Chih ,  Chun-Jung Lin

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C13/004 ,  G11C29/74

Abstract: A magnetoresistive memory stores logic values in high and low resistance states of magnetic tunnel junction elements. Instead of comparing the resistance of elements to a fixed threshold to discern a logic state, the resistances of elements are self-compared before and after imposing a low resistance state. A measure of the resistance of an element in its unknown resistance state is stored, for example by charging a capacitor to a voltage produced when read current bias is applied. Then the element is written into its low resistance state and read current bias is applied again to develop another voltage, representing the low resistance state. A comparison circuit using current summing and an offset providing a minimum difference tolerance determines whether the resistance of the element was changed or remained the same. This determines the logic state of the element.

Abstract translation: 磁阻存储器将逻辑值存储在磁性隧道结元件的高电阻和低电阻状态中。 代替将元件的电阻与固定阈值进行比较以辨别逻辑状态，元件的电阻在施加低电阻状态之前和之后自我比较。 例如，通过将电容器充电到施加读取电流偏压时产生的电压来存储元件在其未知电阻状态下的电阻的量度。 然后将元件写入其低电阻状态，并再次施加读取电流偏压以产生表示低电阻状态的另一电压。 使用电流求和和提供最小差容差的偏移的比较电路确定元件的电阻是改变还是保持相同。 这决定了元素的逻辑状态。