公开(公告)号：US20170188945A1

公开(公告)日：2017-07-06

申请号：US15085531

申请日：2016-03-30

Applicant: Kai Chun Lin ,  Erika Yang

Inventor： Kai Chun Lin ,  Erika Yang

IPC: A61B5/00 ,  A61B5/11 ,  A61B5/0205

CPC classification number: A61B5/4845 ,  A61B5/0205 ,  A61B5/02438 ,  A61B5/026 ,  A61B5/0816 ,  A61B5/1112 ,  A61B5/1118 ,  A61B5/4815 ,  A61B5/681 ,  A61B5/742 ,  A61B5/746 ,  A61B5/7475 ,  A61B2560/0242

Abstract: The embodiments disclose a new type of multi-function smart wristlets, in which a variety of electronic, optoelectronic, and thermal sensors are embedded. These sensors will collect data through various signals from both a person and the environment in order to perform many functions to help people improve their health; it also tells people of the environmental conditions in order for them to make the right decision about their outdoor activities. Also, this wristlet can be a sensor-key to open cars, house doors, garage doors, and so on. It also works as music player to play music in wireless headphones through Bluetooth function on the wristlet. In addition, at night it can also measure your steady heartbeat and blood flow rate along with breathing conditions through the detector sensors. This can monitor a person's health and sleeping quality. This function can also help to alert other family members through an app downloaded on family's phone if a condition appears in sleep or heart rate becomes irregular.

公开(公告)号：US08687412B2

公开(公告)日：2014-04-01

申请号：US13438006

申请日：2012-04-03

Applicant: Yue-Der Chih ,  Chun-Jung Lin ,  Kai-Chun Lin ,  Hung-Chang Yu

Inventor： Yue-Der Chih ,  Chun-Jung Lin ,  Kai-Chun Lin ,  Hung-Chang Yu

IPC: G11C11/00

CPC classification number: G11C11/161 ,  G11C11/1673

Abstract: A reference circuit discerns high or low resistance states of a magneto-resistive memory element such as a bit cell. The reference circuit has magnetic tunnel junction (MTJ) elements in complementary high and low resistance states RH and RL, providing a voltage, current or other parameter for comparison against the memory element to discern a resistance state. The parameter represents an intermediate resistance straddled by RH and RL, such as an average or twice-parallel resistance. The reference MTJ elements are biased from the same read current source as the memory element but their magnetic layers are in opposite order, physically or by order along bias current paths. The reference MTJ elements are biased to preclude any read disturb risk. The memory bit cell is coupled to the same bias polarity source along a comparable path, being safe from read disturb risk in one of its two possible logic states.

Abstract translation: 参考电路识别诸如位单元的磁阻存储元件的高或低电阻状态。 参考电路具有互补的高电阻状态RH和低电阻状态RL的磁隧道结（MTJ）元件，提供用于与存储元件进行比较的电压，电流或其它参数以识别电阻状态。 该参数表示由RH和RL跨过的中间电阻，例如平均或两倍平行的电阻。 参考MTJ元件从与存储元件相同的读取电流源偏置，但它们的磁性层在物理上或沿着偏置电流路径的顺序是相反的顺序。 参考MTJ元件被偏置以排除任何读取干扰风险。 存储器位单元沿着可比较的路径耦合到相同的偏置极性源，在其两种可能的逻辑状态之一中可以避免读取干扰风险。

公开(公告)号：US08570792B2

公开(公告)日：2013-10-29

申请号：US13356920

申请日：2012-01-24

Applicant: Tien-Wei Chiang ,  Kai-Chun Lin ,  Ya-Chen Kao ,  Hung-Chang Yu

Inventor： Tien-Wei Chiang ,  Kai-Chun Lin ,  Ya-Chen Kao ,  Hung-Chang Yu

IPC: G11C11/00 ,  G11C11/14

CPC classification number: H01L27/222 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  H01L43/08

Abstract: A magnetoresistive random access memory (MRAM) cell includes a magnetic tunnel junction (MTJ), a top electrode disposed over the MTJ, a bottom electrode disposed below the MTJ, and an induction line disposed above or below the MTJ. The induction line is configured to induce a magnetic field at the MTJ.

Abstract translation: 磁阻随机存取存储器（MRAM）单元包括磁性隧道结（MTJ），设置在MTJ上方的顶部电极，设置在MTJ下方的底部电极以及设置在MTJ上方或下方的感应线。 感应线被配置为在MTJ处诱导磁场。

公开(公告)号：US20130258762A1

公开(公告)日：2013-10-03

申请号：US13438006

申请日：2012-04-03

Applicant: Yu-Der CHIH ,  Chun-Jung LIN ,  Kai-Chun LIN ,  Hung-Chang YU

Inventor： Yu-Der CHIH ,  Chun-Jung LIN ,  Kai-Chun LIN ,  Hung-Chang YU

IPC: G11C11/16

CPC classification number: G11C11/161 ,  G11C11/1673

Abstract: A reference circuit discerns high or low resistance states of a magneto-resistive memory element such as a bit cell. The reference circuit has magnetic tunnel junction (MTJ) elements in complementary high and low resistance states RH and RL, providing a voltage, current or other parameter for comparison against the memory element to discern a resistance state. The parameter represents an intermediate resistance straddled by RH and RL, such as an average or twice-parallel resistance. The reference MTJ elements are biased from the same read current source as the memory element but their magnetic layers are in opposite order, physically or by order along bias current paths. The reference MTJ elements are biased to preclude any read disturb risk. The memory bit cell is coupled to the same bias polarity source along a comparable path, being safe from read disturb risk in one of its two possible logic states.

Abstract translation: 参考电路识别诸如位单元的磁阻存储元件的高或低电阻状态。 参考电路具有互补的高电阻状态RH和低电阻状态RL的磁隧道结（MTJ）元件，提供用于与存储元件进行比较的电压，电流或其它参数以识别电阻状态。 该参数表示由RH和RL跨过的中间电阻，例如平均或两倍平行的电阻。 参考MTJ元件从与存储元件相同的读取电流源偏置，但它们的磁性层在物理上或沿着偏置电流路径的顺序是相反的顺序。 参考MTJ元件被偏置以排除任何读取干扰风险。 存储器位单元沿着可比较的路径耦合到相同的偏置极性源，在其两种可能的逻辑状态之一中可以避免读取干扰风险。

公开(公告)号：US09058872B2

公开(公告)日：2015-06-16

申请号：US13755445

申请日：2013-01-31

Applicant: Hung-Chang Yu ,  Kai-Chun Lin ,  Yue-Der Chih

Inventor： Hung-Chang Yu ,  Kai-Chun Lin ,  Yue-Der Chih

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/412 ,  G11C14/00

CPC classification number: G11C13/0004 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/412 ,  G11C13/004 ,  G11C13/0069 ,  G11C14/009 ,  G11C2213/79

Abstract: A resistance-based random access memory circuit includes a first data line, a second data line, a plurality of memory cells, a first driving unit, and a second driving unit. The memory cells are arranged one following another in parallel with the first and second data lines. Each of the memory cells are coupled between the first data line and the second data line. The first driving unit is coupled with first ends of the first and second data lines. The first driving unit is configured to electrically couple one of the first data line and the second data line to a first voltage node. The second driving unit is coupled with second ends of the first and second data lines. The second driving unit is configured to electrically couple the other one of the first data line and the second data line to a second voltage node.

Abstract translation: 基于电阻的随机存取存储器电路包括第一数据线，第二数据线，多个存储单元，第一驱动单元和第二驱动单元。 存储单元与第一和第二数据线并行布置。 每个存储器单元耦合在第一数据线和第二数据线之间。 第一驱动单元与第一和第二数据线的第一端耦合。 第一驱动单元被配置为将第一数据线和第二数据线中的一个电耦合到第一电压节点。 第二驱动单元与第一和第二数据线的第二端耦合。 第二驱动单元被配置为将第一数据线和第二数据线中的另一个电耦合到第二电压节点。

公开(公告)号：US08509003B2

公开(公告)日：2013-08-13

申请号：US13237282

申请日：2011-09-20

Applicant: Kai-Chun Lin ,  Hung-Chang Yu ,  Yue-Der Chih

Inventor： Kai-Chun Lin ,  Hung-Chang Yu ,  Yue-Der Chih

IPC: G11C16/06 ,  G11C11/56

CPC classification number: G11C11/5642 ,  G11C11/1673 ,  G11C11/56 ,  G11C11/5607 ,  G11C11/5685 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2013/0057

Abstract: A read architecture for reading random access memory (RAM) cells includes a multi-level sense amplifier, the multi-level sense amplifier including a plurality of sense amplifiers, each sense amplifier having a respective sense threshold and a respective sense output, and a storage module coupled to the multi-level sense amplifier for storing the sense outputs of the multi-level sense amplifier. The storage module stores a first set of sense outputs corresponding to a first read of an RAM cell and stores a second set of sense outputs corresponding to a second read of the RAM cell. The architecture also includes a decision module for comparing the first and second set of sense outputs and determining a data state of the RAM cell based on the comparison.

Abstract translation: 用于读取随机存取存储器（RAM）单元的读取架构包括多电平读出放大器，多电平读出放大器包括多个读出放大器，每个读出放大器具有相应的感测阈值和相应的感测输出，以及存储器 模块耦合到多电平读出放大器，用于存储多电平读出放大器的感测输出。 存储模块存储对应于RAM单元的第一读取的第一组感测输出，并且存储对应于RAM单元的第二读取的第二组感测输出。 该架构还包括用于比较第一和第二组感测输出的判定模块，并且基于该比较确定RAM单元的数据状态。

公开(公告)号：US08493776B1

公开(公告)日：2013-07-23

申请号：US13364756

申请日：2012-02-02

Applicant: Hung-Chang Yu ,  Kai-Chun Lin ,  Yu-Der Chih ,  Chun-Jung Lin

Inventor： Hung-Chang Yu ,  Kai-Chun Lin ,  Yu-Der Chih ,  Chun-Jung Lin

IPC: G11C11/00

CPC classification number: G11C11/1673 ,  G11C13/004 ,  G11C29/74

Abstract: A magnetoresistive memory stores logic values in high and low resistance states of magnetic tunnel junction elements. Instead of comparing the resistance of elements to a fixed threshold to discern a logic state, the resistances of elements are self-compared before and after imposing a low resistance state. A measure of the resistance of an element in its unknown resistance state is stored, for example by charging a capacitor to a voltage produced when read current bias is applied. Then the element is written into its low resistance state and read current bias is applied again to develop another voltage, representing the low resistance state. A comparison circuit using current summing and an offset providing a minimum difference tolerance determines whether the resistance of the element was changed or remained the same. This determines the logic state of the element.

Abstract translation: 磁阻存储器将逻辑值存储在磁性隧道结元件的高电阻和低电阻状态中。 代替将元件的电阻与固定阈值进行比较以辨别逻辑状态，元件的电阻在施加低电阻状态之前和之后自我比较。 例如，通过将电容器充电到施加读取电流偏压时产生的电压来存储元件在其未知电阻状态下的电阻的量度。 然后将元件写入其低电阻状态，并再次施加读取电流偏压以产生表示低电阻状态的另一电压。 使用电流求和和提供最小差容差的偏移的比较电路确定元件的电阻是改变还是保持相同。 这决定了元素的逻辑状态。

公开(公告)号：US20130070519A1

公开(公告)日：2013-03-21

申请号：US13237282

申请日：2011-09-20

Applicant: Kai-Chun Lin ,  Hung-Chang Yu ,  Yue-Der Chih

Inventor： Kai-Chun Lin ,  Hung-Chang Yu ,  Yue-Der Chih

IPC: G11C11/16

CPC classification number: G11C11/5642 ,  G11C11/1673 ,  G11C11/56 ,  G11C11/5607 ,  G11C11/5685 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2013/0057

Abstract: A read architecture for reading random access memory (RAM) cells includes a multi-level sense amplifier, the multi-level sense amplifier including a plurality of sense amplifiers, each sense amplifier having a respective sense threshold and a respective sense output, and a storage module coupled to the multi-level sense amplifier for storing the sense outputs of the multi-level sense amplifier. The storage module stores a first set of sense outputs corresponding to a first read of an RAM cell and stores a second set of sense outputs corresponding to a second read of the RAM cell. The architecture also includes a decision module for comparing the first and second set of sense outputs and determining a data state of the RAM cell based on the comparison.

Abstract translation: 用于读取随机存取存储器（RAM）单元的读取架构包括多电平读出放大器，多电平读出放大器包括多个读出放大器，每个读出放大器具有相应的感测阈值和相应的感测输出，以及存储器 模块耦合到多电平读出放大器，用于存储多电平读出放大器的感测输出。 存储模块存储对应于RAM单元的第一读取的第一组感测输出，并且存储对应于RAM单元的第二读取的第二组感测输出。 该架构还包括用于比较第一和第二组感测输出的判定模块，并且基于该比较确定RAM单元的数据状态。

公开(公告)号：US08902641B2

公开(公告)日：2014-12-02

申请号：US13443056

申请日：2012-04-10

Applicant: Yue-Der Chih ,  Chin-Yi Huang ,  Chun-Jung Lin ,  Kai-Chun Lin ,  Hung-Chang Yu

Inventor： Yue-Der Chih ,  Chin-Yi Huang ,  Chun-Jung Lin ,  Kai-Chun Lin ,  Hung-Chang Yu

IPC: G11C11/16 ,  G11C11/15

CPC classification number: G11C11/16 ,  G11C11/15 ,  G11C11/1673

Abstract: Magneto-resistive memory bit cells in an array have high or low resistance states storing logic values. During read operations, a bias source is coupled to an addressed memory word, coupling a parameter related to cell resistance to a sense amplifier at each bit position. The sense amplifiers determine whether the parameter value is greater or less than a reference value between the high and low resistance states. The reference value is derived by averaging or splitting a difference of resistances of reference cells at high and/or low resistance states. Bias current is conducted over address lines with varying resistance, due to different distances between the sense amplifiers and addressed memory words, which is canceled by inserting into the comparison circuit a resistance from a dummy addressing array, equal to the resistance of the conductor addressing the selected word line and bit position.

Abstract translation: 阵列中的磁阻存储器位单元具有存储逻辑值的高或低电阻状态。 在读取操作期间，偏置源耦合到寻址的存储器字，将与单元电阻相关的参数耦合到每个位位置的读出放大器。 读出放大器确定参数值是大于还是小于高电阻状态和低电阻状态之间的参考值。 参考值是通过在高和/或低电阻状态下对参考电池的电阻差进行平均或分割得出的。 由于感测放大器和寻址的存储器字之间的距离不同，偏置电流在具有变化的电阻的地址线上进行，这通过将来自虚拟寻址阵列的电阻插入到比较电路中而被抵消，等于导体寻址的电阻 选择的字线和位位置。

公开(公告)号：US20140211537A1

公开(公告)日：2014-07-31

申请号：US13755445

申请日：2013-01-31

Applicant: Hung-Chang YU ,  Kai-Chun LIN ,  Yue-Der CHIH

Inventor： Hung-Chang YU ,  Kai-Chun LIN ,  Yue-Der CHIH

IPC: G11C13/00

CPC classification number: G11C13/0004 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/412 ,  G11C13/004 ,  G11C13/0069 ,  G11C14/009 ,  G11C2213/79

Abstract: A resistance-based random access memory circuit includes a first data line, a second data line, a plurality of memory cells, a first driving unit, and a second driving unit. The memory cells are arranged one following another in parallel with the first and second data lines. Each of the memory cells are coupled between the first data line and the second data line. The first driving unit is coupled with first ends of the first and second data lines. The first driving unit is configured to electrically couple one of the first data line and the second data line to a first voltage node. The second driving unit is coupled with second ends of the first and second data lines. The second driving unit is configured to electrically couple the other one of the first data line and the second data line to a second voltage node.

Abstract translation: 基于电阻的随机存取存储器电路包括第一数据线，第二数据线，多个存储单元，第一驱动单元和第二驱动单元。 存储单元与第一和第二数据线并行布置。 每个存储器单元耦合在第一数据线和第二数据线之间。 第一驱动单元与第一和第二数据线的第一端耦合。 第一驱动单元被配置为将第一数据线和第二数据线中的一个电耦合到第一电压节点。 第二驱动单元与第一和第二数据线的第二端耦合。 第二驱动单元被配置为将第一数据线和第二数据线中的另一个电耦合到第二电压节点。