公开(公告)号：US5103419A

公开(公告)日：1992-04-07

申请号：US473760

申请日：1990-02-02

Applicant: Masaki Toyokura ,  Kunitoshi Aono ,  Toshiyuki Araki

Inventor： Masaki Toyokura ,  Kunitoshi Aono ,  Toshiyuki Araki

IPC: G06F7/544

CPC classification number: G06F7/5443 ,  G06F7/49994

Abstract: A sum-of-products calculating circuit includes a bit extension circuit, wherein the most significant bit of an intermediate result of the multiplication effected by a multiplier is extended from an order one bit of the order higher than that of the most significant bit of the intermediate result of the multiplication to the sign bit of addition input data to an adder, by using the most significant bit of each of two intermediate results of the multiplication effected by a multiplier and the sign bit of each of multiplication input data to the multiplier. The data having the extended data bits are inputted to an adder as addition data for the addition performed therein. Thereby, the number of bits used for representing output data of the multiplier can be equalized with that of bits used for representing input data of the adder by a simple logic circuit without the addition of dummy bits to the addition data. Thus, the component elements of the calculating circuit is substantially reduced in number.

Abstract translation: 产品总计算电路包括比特扩展电路，其中由乘法器执行的乘法的中间结果的最高有效位从比该位的最高有效位的顺序的一位高的顺序扩展 通过使用由乘法器实现的乘法的两个中间结果中的每一个的最高有效位和乘法输入数据的乘法符号位乘以乘法运算到加法器的相加输入数据的符号位的中间结果。 将具有扩展数据位的数据作为加法执行的加法数据输入加法器。 因此，用于表示乘法器的输出数据的比特数可以与用于通过简单逻辑电路表示加法器的输入数据的比特的比特相加，而不对加法数据添加伪比特。 因此，计算电路的组成元件的数量显着减少。

公开(公告)号：US4845767A

公开(公告)日：1989-07-04

申请号：US266893

申请日：1988-11-03

Applicant: Toshiki Mori ,  Haruyasu Yamada ,  Kunitoshi Aono ,  Masakatsu Maruyama

Inventor： Toshiki Mori ,  Haruyasu Yamada ,  Kunitoshi Aono ,  Masakatsu Maruyama

IPC: G06T5/20

CPC classification number: G06T5/20

Abstract: An image signal processor which includes a local image register for receiving local image area data of m rows.times.n columns pixels, and a expansion use register of m row.times.1 column pixels coupled to the output of the local image register. Thereby, expansion of local image area, and parallel processing can be readily conducted.

Abstract translation: 一种图像信号处理器，其包括用于接收m行×x列像素的本地图像区域数据的本地图像寄存器和耦合到本地图像寄存器的输出的m row×1列像素的扩展使用寄存器。 因此，可以容易地进行局部图像区域的扩展和并行处理。

公开(公告)号：US6026486A

公开(公告)日：2000-02-15

申请号：US859308

申请日：1997-05-20

Applicant: Hisashi Kodama ,  Kunitoshi Aono

Inventor： Hisashi Kodama ,  Kunitoshi Aono

IPC: G06F9/318 ,  G06F9/38 ,  G06F9/30 ,  G06F15/16

CPC classification number: G06F9/3822 ,  G06F9/30076 ,  G06F9/30149 ,  G06F9/30174 ,  G06F9/30178 ,  G06F9/30189 ,  G06F9/3802 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3885

Abstract: A 32-bit processor control unit receives from a memory an instruction. The control unit then determines whether the received instruction is intended for a 32-bit processor or for a 16-bit processor. If the received instruction is analyzed to be a 32-bit processor instruction, the control unit controls the 32-bit processor with the aid of two 16-bit instruction control units. If the received instruction is a 16-bit processor instruction, the 32-bit processor control unit sends a 16-bit processor mode signal to each of the 16-bit instruction control units. One of the two 16-bit instruction control units controls one of two 16-bit processors which are divisions of the 32-bit processor while the other 16-bit instruction control unit controls the other 16-bit processor. The present invention makes it possible to have a single, wide bitwidth processor serve as a plurality of narrow bitwidth processors depending upon the type of processing. Various operations can be performed in parallel, thereby improving processor performance.

Abstract translation: 32位处理器控制单元从存储器接收指令。 然后，控制单元确定接收到的指令是针对32位处理器还是针对16位处理器。 如果接收到的指令被分析为32位处理器指令，则控制单元借助于两个16位指令控制单元控制32位处理器。 如果接收到的指令是16位处理器指令，则32位处理器控制单元向16位指令控制单元中的每一个发送16位处理器模式信号。 两个16位指令控制单元之一控制两个16位处理器中的一个，它们是32位处理器的分区，而另一个16位指令控制单元控制另一个16位处理器。 本发明使得可以根据处理的类型使单个宽的位宽处理器用作多个窄位宽处理器。 可以并行执行各种操作，从而提高处理器的性能。

公开(公告)号：US5299320A

公开(公告)日：1994-03-29

申请号：US752787

申请日：1991-08-30

Applicant: Kunitoshi Aono ,  Masaki Toyokura ,  Toshiyuki Araki ,  Akihiko Ohtani ,  Hisashi Kodama ,  Kiyoshi Okamoto

Inventor： Kunitoshi Aono ,  Masaki Toyokura ,  Toshiyuki Araki ,  Akihiko Ohtani ,  Hisashi Kodama ,  Kiyoshi Okamoto

IPC: G06F9/345 ,  G06F9/38 ,  G06F15/78 ,  G06F9/30

CPC classification number: G06F15/8076 ,  G06F9/30036 ,  G06F9/345 ,  G06F9/3885

Abstract: In a program control type processor for executing plural instructions including a vector pipeline instruction including a data processor for executing a pipeline operation, there is provided a program controller including a program memory, a program counter and a decoder, and is further provided an address generator and a data memory. When the vector pipeline instruction is read out from the program memory and is decoded by the decoder, the program controller stops the program counter and outputs a start signal, and thereafter, controls an operation of the data processor according to the contents of the vector pipeline instruction. The data processor executes the pipeline operation for the data outputted from the data memory by being controlled by the program controller, and the program controller detects completion of the pipeline operation performed in response to the vector pipeline instruction a predetermined number of cycles after receiving the end signal, and thereafter, sequentially executes instructions following the vector pipeline instruction.

Abstract translation: 在用于执行包括包括用于执行流水线操作的数据处理器的向量流水线指令的多个指令的程序控制类型处理器中，提供了一种程序控制器，其包括程序存储器，程序计数器和解码器，并且还提供有地址生成器 和数据存储器。 当从程序存储器中读出向量流水线指令并由解码器解码时，程序控制器停止程序计数器并输出起始信号，然后根据向量管线的内容来控制数据处理器的操作 指令。 数据处理器通过由程序控制器控制从数据存储器输出的数据执行流水线操作，并且程序控制器在接收到结束之后响应于向量流水线指令检测预定数量的循环执行的流水线操作的完成 信号，然后依次执行向量流水线指令之后的指令。