公开(公告)号：US06501398B2

公开(公告)日：2002-12-31

申请号：US09815269

申请日：2001-03-23

申请人： Masaki Toyokura

发明人： Masaki Toyokura

IPC分类号： H03M700

CPC分类号： H03M7/40 ,  H03M7/42

摘要： A variable-length code decoder sequentially decodes a series of variable-length codewords included in a bit stream and outputs decoded symbols corresponding to the codewords. The decoder includes an interface section and a decoding section. The interface section accumulates various code lengths of the decoded codewords to obtain a sum. Next, the interface section selects an N-bit contiguous data sequence (where N is a maximum code length of the codewords) from a 2N- or (2N−1)-bit contiguous data sequence, included in the bit stream, in accordance with the sum and outputs the N-bit contiguous data sequence. The decoding section receives the output of the interface section and decodes a codeword included in a combination of the output and a previous output of the interface section by reference to a lookup table, thereby obtaining and outputting a decoded symbol and outputting a code length of the decoded codeword to the interface section.

摘要翻译： 可变长度码解码器对包括在比特流中的一系列可变长度码字进行顺序解码，并输出对应于码字的解码符号。 解码器包括接口部分和解码部分。 接口部分累积解码码字的各种码长以获得和。 接下来，接口部分根据比特流中包含的2N或（2N-1）位连续的数据序列，选择N位连续数据序列（其中N是码字的最大码长） 并且输出N位连续的数据序列。 解码部分接收接口部分的输出，并通过参考查找表对接口部分的输出和先前输出的组合中包括的码字进行解码，从而获得并输出解码符号并输出解码部分的代码长度 解码码字到接口部分。

公开(公告)号：US5293596A

公开(公告)日：1994-03-08

申请号：US658154

申请日：1991-02-20

申请人： Masaki Toyokura ,  Kunitoshi Aono ,  Toshiyuki Araki

发明人： Masaki Toyokura ,  Kunitoshi Aono ,  Toshiyuki Araki

IPC分类号： G06F12/02 ,  G06F12/00

CPC分类号： G06F12/0207

摘要： A multidimensional address generator for generating one-dimensional addresses respectively corresponding to P.sub.1 .times.P.sub.2 .times. . . . .times.P.sub.N data of a predetermined region of an N-dimensional entire data array (N is a positive integer larger than one) which has Q.sub.1 .times.Q.sub.2 .times. . . . .times.Q.sub.N data (P.sub.1, . . . and P.sub.N and Q.sub.1, . . . and Q.sub.N are positive integers and P.sub.1 .ltoreq.Q.sub.1, . . . and P.sub.N .ltoreq.Q.sub.N). The generator comprises a first to third multiplexers, an adder and a first to Nth accumulating registers. In the generator, the first multiplexer selects one of a first to Nth increments respectively corresponding to a first to Nth directions, in which data to successively be accessed are arranged. Further, the second multiplexer selects one of data stored in the first to Nth accumulating registers, and the third multiplexer selects between the start address and an output of the adder. Moreover, data selected by the first multiplexer is added by the adder to data selected by the second multiplexer, and data selected by the third multiplexer is inputted to the first to Nth accumulating registers. Furthermore, a start address is written to the first to Nth accumulating registers when the address generator is activated. Moreover, the first increment is added to the data held in the first accumulating register in each of Cycles 1 to (P.sub.1 -1) and . . . and Cycles (P.sub.N P.sub.N-1 . . . P.sub.2 -1)P.sub.1 +1 to (P.sub.N P.sub.N-1 . . . P.sub.2 P.sub.1 -1), the first increment is added to the data held in the first accumulating register, and a result is written thereto. Additionally, an nth increment (n=2, 3, . . . , N) is added to the data held in the nth accumulating register, and a result is written to the first to nth accumulating registers, every P.sub.n-1 P.sub.n-2 . . . P.sub.1 cycles during Cycles P.sub.n P.sub.n-1 P.sub.n-2 . . . P.sub.1 to (P.sub.n -1)P.sub.n-1 P.sub.n-2 . . . P.sub.1 and so on. The data finally obtained in the first accumulating register is outputted. Consequently, an operation of accessing a plurality of multidimensional data can be performed easily and quickly.

公开(公告)号：US20120020642A1

公开(公告)日：2012-01-26

申请号：US13253562

申请日：2011-10-05

申请人： Masaki TOYOKURA

发明人： Masaki TOYOKURA

IPC分类号： H04N9/80

CPC分类号： H04N5/775 ,  G11B20/10527 ,  G11B27/034 ,  G11B2020/10546 ,  H04N9/802 ,  H04N21/4325 ,  H04N21/4334 ,  H04N21/4394 ,  H04N21/44016 ,  H04N21/454

摘要： A data recorder records (n−1)th episode data and n-th episode data of a drama series, where n is an integer of two ore more. An audio decoder generates respective audio data of these episodes. An overlapping portion determiner extracts and compares a tail portion of the audio data of the (n−1)th episode and a head portion of the audio data of the n-th episode to detect an overlapping portion, and records an overlapping time between the (n−1)th and n-th episodes to an overlapping time storage. A recorded data editor deletes a portion of the (n−1)th episode data corresponding to the overlapping time recorded in the overlapping time storage, from a tail end of the (n−1)th episode data, and records the resulting (n−1)th episode data as (n−1)th episode edited data to the data recorder.

摘要翻译： 数据记录器记录戏剧系列（n-1）剧集数据和第n集剧情数据，其中n是两个以上的整数。 音频解码器产生这些情节的相应音频数据。 重叠部分确定器提取并比较第（n-1）事件的音频数据的尾部与第n集的音频数据的头部，以检测重叠部分，并记录重叠部分之间的重叠时间 （n-1）次和第n次发作到重叠时间存储。 记录数据编辑器从第（n-1）个剧集数据的尾端删除与在重叠时间存储中记录的重叠时间相对应的第（n-1）个剧集数据的一部分，并记录所得到的（n -1）发作数据作为第（n-1）次编辑数据到数据记录器。

公开(公告)号：US07231477B2

公开(公告)日：2007-06-12

申请号：US10802933

申请日：2004-03-18

申请人： Masaki Toyokura

发明人： Masaki Toyokura

IPC分类号： G06F13/14

CPC分类号： G06F13/1605

摘要： A bus controller is provided including a processing means for performing processings of levels having cycle numbers which are different dependent on requesters which respectively issue an access request to a common memory. When it is expected from the present cycle number that a limit cycle number is exceeded, the bus controller selects a processing level with which the processing is performed with a smaller cycle number, or performs a control of giving no permission to a non-realtime bus access request. Thereby, it is possible to design a system with a cycle number that is smaller than the total sum of the maximum access cycle numbers multiplied by the maximum access times over all requesters.

摘要翻译： 提供了一种总线控制器，其包括处理装置，用于执行具有不同的循环数的电平的处理，这取决于请求者，所述请求者分别向公共存储器发出访问请求。 当从当前循环次数预期超过限制循环数时，总线控制器以较小的循环次数选择执行处理的处理级别，或执行不对非实时总线的许可的控制 访问请求。 因此，可以设计一个周期数小于最大访问周期数乘以所有请求者的最大访问时间的总和的系统。

公开(公告)号：US06320906B1

公开(公告)日：2001-11-20

申请号：US08859428

申请日：1997-05-20

申请人： Masaki Toyokura ,  Takuya Jinbo

发明人： Masaki Toyokura ,  Takuya Jinbo

IPC分类号： H04N712

CPC分类号： H04N19/533 ,  H04N5/145 ,  H04N19/57

摘要： In an animation encoding process, a motion vector which can minimize an AC component included in a discrete cosine transform result is detected. For this purpose, a block X (i, j) to be processed is extracted from an input image X, and a prospective reference block Yk (i, J) is extracted from a reference image Y, wherein k is an integer depending upon the size of a motion vector search range, i=0, . . . , or 3, and j=0, . . . , or 63. From each pixel value in each sub block (including 8×8 pixels) of the block to be processed, an average value Xa (i) of pixels in the sub block is subtracted, and from each pixel value in each sub block (including 8×8 pixels) of the prospective reference block, an average value Yka (i) of pixels in the sub block is subtracted. Then, an evaluation value Sk for block matching is calculated. The prospective reference block having the minimum evaluation value is selected as a reference block among the plural prospective reference blocks, so as to obtain a motion vector V corresponding to the positional relationship between the block to be processed and the reference block.

摘要翻译： 在动画编码处理中，检测出可以最小化包含在离散余弦变换结果中的AC分量的运动矢量。 为此，从输入图像X提取要处理的块X（i，j），并从参考图像Y提取预期参考块Y k（i，j），其中k是取决于 运动矢量搜索范围的大小，i = 0，。 。 。 ，或3，并且j = 0。 。 。 或63.根据要处理的块的每个子块（包括8×8像素）中的每个像素值，减去子块中的像素的平均值Xa（i），并且从每个子块中的每个像素值（ 包括8×8像素），减去子块中的像素的平均值Yka（i）。 然后，计算块匹配的评价值Sk。 在多个预期参考块中选择具有最小评估值的预期参考块作为参考块，以获得与待处理块和参考块之间的位置关系相对应的运动矢量V.

公开(公告)号：US5583803A

公开(公告)日：1996-12-10

申请号：US364116

申请日：1994-12-27

申请人： Yoshifumi Matsumoto ,  Masaki Toyokura

发明人： Yoshifumi Matsumoto ,  Masaki Toyokura

IPC分类号： G06F17/14 ,  G06F7/38

CPC分类号： G06F17/147

摘要： The two-dimensional DCT (discrete cosine transform) of plural n.times.n data items is carried out at high speed, with requiring less hardware. X(h) is an operation in which row vectors of A(h) are sequentially transmitted from a first memory to a one-dimensional DCT processor for product-of-matrices computations and the products thus found are sequentially written to at addresses of corresponding row vectors of B(h) of a second memory. Y(h) is an operation in which column vectors of B(h) are sequentially transmitted from the second memory to the one-dimensional DCT processor for product-of-matrices computations and the products thus found are sequentially written to at addresses of corresponding column vectors of C(h) of the first memory. The operation X(h) starts at h=1 and ends at h=m. Then, the operation Y(h) starts at h=1 and ends at h=m. The one-dimensional DCT processor performs the pipelining operation of n-element one-dimensional vectors for product-of-matrices computations.

摘要翻译： 多个nxn数据项的二维DCT（离散余弦变换）以较高的速度执行，需要较少的硬件。 X（h）是对于矩阵的乘积运算，从第一存储器向一维DCT处理器依次发送A（h）的行向量的操作，并且将如此找到的乘积顺序地写入对应的地址 第二存储器的B（h）的行向量。 Y（h）是从第二存储器向一维DCT处理器顺序发送B（h）的列向量到矩阵计算的操作，并且将如此找到的乘积顺序写入到相应的地址 第一存储器的C（h）的列向量。 操作X（h）从h = 1开始，以h = m结束。 然后，操作Y（h）从h = 1开始，以h = m结束。 一维DCT处理器执行用于矩阵计算的n元素一维向量的流水线操作。

公开(公告)号：US5432726A

公开(公告)日：1995-07-11

申请号：US251311

申请日：1994-05-31

申请人： Shun-ichi Kurohmaru ,  Hisashi Kodama ,  Toshiyuki Araki ,  Masaki Toyokura

发明人： Shun-ichi Kurohmaru ,  Hisashi Kodama ,  Toshiyuki Araki ,  Masaki Toyokura

IPC分类号： G06F7/505 ,  G06F7/00 ,  G06F7/50 ,  G06F9/302 ,  G06F9/305 ,  G06F9/32 ,  G06F17/10 ,  G06T9/00 ,  H03M7/30 ,  H04N19/00 ,  H04N19/42 ,  H04N19/436 ,  G06K9/36

CPC分类号： G06F7/5055 ,  G06F9/3001 ,  G06F9/30058 ,  H04N19/45 ,  H04N19/60

摘要： Two sets of input data A and B are provided. A first selector circuit outputs either the most significant bit of the input data B or the inversion thereof, in accordance with a control signal which has been sent thereto through a control line. An adder adds 1 to the least significant bit of the input data B, and also adds the output from the first selector circuit to all the other bits thereof. A zero-judgment circuit judges whether the input data B is 0 or not, and then, if it is 0, sets a flag to a predetermined value. A selector-control circuit allows a second selector circuit to select the input data B in the case where the least significant bit of the input data A is 1 or the flag from the zero-judgment circuit is set to the predetermined value, and to select, in the other cases, the output from the adder. In this manner, a conditional branch operation required for quantization and inverse quantization of data is executed at high speed, which operation involves either adding 1 to or subtracting 1 from the input data B to output the result, or outputting the input data B, depending on whether the input data B is positive, negative or zero, and also depending on whether the input data A is an even number or an odd number.

摘要翻译： 提供两组输入数据A和B。 第一选择器电路根据通过控制线发送给它的控制信号输出输入数据B的最高有效位或其反相。 加法器将1加到输入数据B的最低有效位，并将第一选择器电路的输出加到其它所有位。 零判断电路判断输入数据B是否为0，然后如果为0则将标志设置为预定值。 选择器控制电路允许第二选择器电路在输入数据A的最低有效位为1或来自零判断电路的标志被设置为预定值的情况下选择输入数据B，并且选择 在其他情况下，来自加法器的输出。 以这种方式，高速执行量化和数据逆量化所需的条件分支操作，该操作涉及从输入数据B中加1或减1以输出结果，或输出输入数据B，依赖 关于输入数据B是正还是负，还取决于输入数据A是偶数还是奇数。

公开(公告)号：US5278781A

公开(公告)日：1994-01-11

申请号：US51273

申请日：1993-04-23

申请人： Kunitoshi Aono ,  Masaki Toyokura ,  Shiro Sakiyama ,  Toshiyuki Araki ,  Masakatsu Maruyama

发明人： Kunitoshi Aono ,  Masaki Toyokura ,  Shiro Sakiyama ,  Toshiyuki Araki ,  Masakatsu Maruyama

IPC分类号： G06F7/544 ,  G06F17/10 ,  G06F7/38

CPC分类号： G06F7/5443 ,  G06F17/10 ,  G06F2207/3884

摘要： A digital signal processing system includes a plurality of multiplier/accumulators for executing a pipeline processing operation. Each of the plurality of multiplier/accumulators includes a multiplication part and an addition part. The multiplication parts includes N pipeline registers for storing N intermediate outputs of a multiplier. The addition part includes a Wallace tree transformation unit for transforming a sum of N+1 inputs into two transformation outputs, and an adder for adding the two transformation outputs. The N+1 inputs includes the N intermediate outputs from the multiplication part and the one addition output from the adder.

摘要翻译： 数字信号处理系统包括用于执行流水线处理操作的多个乘法器/累加器。 多个乘法器/累加器中的每一个包括乘法部分和加法部分。 乘法部分包括用于存储乘法器的N个中间输出的N个流水线寄存器。 加法部分包括用于将N + 1个输入的和转换为两个变换输出的华莱士树变换单元和用于将两个变换输出相加的加法器。 N + 1输入包括来自乘法部分的N个中间输出和来自加法器的一个相加输出。

公开(公告)号：US5103419A

公开(公告)日：1992-04-07

申请号：US473760

申请日：1990-02-02

申请人： Masaki Toyokura ,  Kunitoshi Aono ,  Toshiyuki Araki

发明人： Masaki Toyokura ,  Kunitoshi Aono ,  Toshiyuki Araki

IPC分类号： G06F7/544

CPC分类号： G06F7/5443 ,  G06F7/49994

摘要： A sum-of-products calculating circuit includes a bit extension circuit, wherein the most significant bit of an intermediate result of the multiplication effected by a multiplier is extended from an order one bit of the order higher than that of the most significant bit of the intermediate result of the multiplication to the sign bit of addition input data to an adder, by using the most significant bit of each of two intermediate results of the multiplication effected by a multiplier and the sign bit of each of multiplication input data to the multiplier. The data having the extended data bits are inputted to an adder as addition data for the addition performed therein. Thereby, the number of bits used for representing output data of the multiplier can be equalized with that of bits used for representing input data of the adder by a simple logic circuit without the addition of dummy bits to the addition data. Thus, the component elements of the calculating circuit is substantially reduced in number.

摘要翻译： 产品总计算电路包括比特扩展电路，其中由乘法器执行的乘法的中间结果的最高有效位从比该位的最高有效位的顺序的一位高的顺序扩展 通过使用由乘法器实现的乘法的两个中间结果中的每一个的最高有效位和乘法输入数据的乘法符号位乘以乘法运算到加法器的相加输入数据的符号位的中间结果。 将具有扩展数据位的数据作为加法执行的加法数据输入加法器。 因此，用于表示乘法器的输出数据的比特数可以与用于通过简单逻辑电路表示加法器的输入数据的比特的比特相加，而不对加法数据添加伪比特。 因此，计算电路的组成元件的数量显着减少。

公开(公告)号：US5596518A

公开(公告)日：1997-01-21

申请号：US434298

申请日：1995-05-03

申请人： Masaki Toyokura ,  Kiyoshi Okamoto ,  Yoshifumi Matsumoto

发明人： Masaki Toyokura ,  Kiyoshi Okamoto ,  Yoshifumi Matsumoto

IPC分类号： G06F7/544 ,  G06F17/14

CPC分类号： G06F17/147 ,  G06F7/5443

摘要： Stored in each of four coefficient memories are eight elements of each row of a matrix in 4 rows and 8 columns, which matrix consists of absolute values of elements of upper four rows out of an inverse discrete cosine matrix in 8 rows and 8 columns to be subjected to an 8-point IDCT processing. An input element y.sub.ij is supplied in parallel to four multipliers. Each of the four multipliers executes multiplication of an output of the corresponding coefficient memory out of the four coefficient memories, by the input element y.sub.ij. Eight accumulators are disposed for executing, in parallel, accumulation for obtaining eight inner products using results of the four multipliers while restoring signs of the coefficients of the orthogonal transform matrix. An 8-input selector is disposed for successively selecting results of the eight accumulators to supply an inner product w.sub.ij corresponding to the input element y.sub.ij.

摘要翻译： 存储在四个系数存储器的每一个中的是四行和八列中矩阵的每一行的八个元素，该矩阵由8行和8列中的反离散余弦矩阵中的上四行的元素的绝对值组成 经过8点IDCT处理。 输入元素yij并行提供给四个乘法器。 四个乘法器中的每一个由输入元件yij执行四个系数存储器中的对应系数存储器的输出的乘法。 八个累加器被设置为并行执行累积，以使用四个乘法器的结果来获得八个内积，同时恢复正交变换矩阵的系数的符号。 设置8输入选择器，用于连续选择八个累加器的结果，以提供对应于输入元件yij的内积wij。