公开(公告)号：US4635231A

公开(公告)日：1987-01-06

申请号：US662900

申请日：1984-10-19

Applicant: Toshiki Mori ,  Haruyasu Yamada ,  Kenichi Hasegawa ,  Kunitoshi Aono

Inventor： Toshiki Mori ,  Haruyasu Yamada ,  Kenichi Hasegawa ,  Kunitoshi Aono

IPC: G11C7/10 ,  G11C11/411 ,  G11C11/416 ,  G11C11/40

CPC classification number: G11C11/4116 ,  G11C11/416 ,  G11C7/1024

Abstract: To extend the function of a bipolar type RAM, a register function is added to the RAM function. The register function is such that the contents stored in a memory cell is inputted to a differential switch, and the output to the differential switch is derived out to constantly read out the stored content of a desired bit with a simple circuit construction.

Abstract translation: 为了扩展双极型RAM的功能，将寄存器功能添加到RAM功能。 寄存器功能使得存储在存储单元中的内容被输入到差分开关，并且导出差分开关的输出，以通过简单的电路结构不断地读出存储的所需位的内容。

公开(公告)号：US5499348A

公开(公告)日：1996-03-12

申请号：US266104

申请日：1994-06-27

Applicant: Toshiyuki Araki ,  Kunitoshi Aono ,  Masaki Toyokura

Inventor： Toshiyuki Araki ,  Kunitoshi Aono ,  Masaki Toyokura

IPC: G06F9/38

CPC classification number: G06F9/3824

Abstract: The digital processor includes an instruction memory, a sequencer, a decoder, and a memory reference control circuit. In case the sequencer reads the external memory reference instruction, the memory reference control circuit serves to fetch an external memory reference instruction signal and an operand of the external memory reference signal delivered from the decoder, hold the operand until the external memory cycle executed by the external memory reference instruction is terminated, and release the operand when the cycle is terminated. The sequencer serves to have succeeding instructions read out continuously while the external memory reference instruction is being executed, and to concurrently execute the read-out instructions when the read-out instructions refer to resources not occupied by the external memory reference instruction, so as to execute the read-out instructions in parallel with the external memory reference instruction, thereby improving the throughput of the total processing.

Abstract translation: 数字处理器包括指令存储器，定序器，解码器和存储器参考控制电路。 在定序器读取外部存储器参考指令的情况下，存储器参考控制电路用于获取从解码器传送的外部存储器参考指令信号和外部存储器参考信号的操作数，保持操作数直到由 外部存储器参考指令终止，并且在循环终止时释放操作数。 当执行外部存储器参考指令时，定序器用于连续地读出后续指令，并且当读出指令参考未被外部存储器参考指令占用的资源时，同时执行读出指令，以便 执行与外部存储器参考指令并行的读出指令，从而提高总处理的吞吐量。

公开(公告)号：US4635292A

公开(公告)日：1987-01-06

申请号：US682321

申请日：1984-12-17

Applicant: Toshiki Mori ,  Haruyasu Yamada ,  Kenichi Hasegawa ,  Kunitoshi Aono

Inventor： Toshiki Mori ,  Haruyasu Yamada ,  Kenichi Hasegawa ,  Kunitoshi Aono

IPC: G06T5/20 ,  G06F9/28 ,  G06F15/66 ,  G06K9/36

CPC classification number: G06T5/20

Abstract: This invention provides parallel partial image processing such as spatial convolution or non-linear neighbor arithmetic operation using an image processor which can easily be formed as a large-scale integrated circuit and can be used for various purposes. The image processor has an adder-subtractor, a multiplier, a reciprocal number memory in which the reciprocal of an address and the amount of shift are stored at each address, and a shift register. The processor therefore is capable of high-speed dividing operations by multiplying a multiplicant by the reciprocal of a multiplier and by shifting the result of the multiplication. Also, by switching the inputs to the adder-subtractor and to the multiplier rapidly under program control, it is possible to perform arbitrary addition, subtraction, multiplication and division on partial image data of m rows and n columns stored in a partial image memory of the image processor.

Abstract translation: 本发明提供并行部分图像处理，例如使用可以容易地形成为大规模集成电路并可用于各种目的的图像处理器的空间卷积或非线性相邻算术运算。 图像处理器具有加法器 - 减法器，乘法器，互易数存储器，其中地址的倒数和移位量存储在每个地址处，以及移位寄存器。 因此，处理器能够通过将乘数乘以乘法器的倒数并通过移位乘法结果来进行高速分频操作。 此外，通过在程序控制下将输入切换到加法器 - 减法器和乘法器，可以对存储在部分图像存储器中的m行和n列的部分图像数据执行任意加法，减法，乘法和除法 图像处理器。

公开(公告)号：US20100321982A1

公开(公告)日：2010-12-23

申请号：US12867392

申请日：2009-12-16

Applicant: Takeshi Takagi ,  Shunsaku Muraoka ,  Ryotaro Azuma ,  Kunitoshi Aono

Inventor： Takeshi Takagi ,  Shunsaku Muraoka ,  Ryotaro Azuma ,  Kunitoshi Aono

IPC: G11C11/00 ,  G11C7/00

CPC classification number: H01L27/101 ,  G11C13/0002 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1675

Abstract: To provide a nonvolatile storage device (100) which is capable of achieving stable operation and includes variable resistance elements. The nonvolatile storage device (100) includes: memory cells (M111, M112, . . . ) each of which is provided at three-dimensional cross-points between word lines (WL0, WL1, . . . ) and bit lines (BL0, BL1, . . . ) and having a resistance value that reversibly changes based on an electrical signal; a row selection circuit-and-driver (103) provided with transistors (103a) each of which applies a predetermined voltage to a corresponding one of the word lines (WL0, WL1, . . . ); a column selection circuit-and-driver (104) provided with transistors (104a) each of which applies a predetermined voltage to a corresponding one of the bit lines (BL0, BL1, . . . ); and a substrate bias circuit (110) which applies a forward bias voltage to a substrate of such transistors (103a and 104a).

Abstract translation: 提供能够实现稳定操作并且包括可变电阻元件的非易失性存储装置（100）。 非易失性存储装置（100）包括：存储单元（M111，M112 ...），每个存储单元设置在字线（WL0，WL1 ...）与位线（BL0， BL1，...），并且具有基于电信号可逆地改变的电阻值; 具有晶体管（103a）的行选择电路驱动器（103），每个晶体管将预定电压施加到对应的一个字线（WL0，WL1 ...）; 具有晶体管（104a）的列选择电路驱动器（104），每个晶体管将预定电压施加到相应的位线（BL0，BL1 ...）中; 以及向这种晶体管（103a和104a）的衬底施加正向偏置电压的衬底偏置电路（110）。

公开(公告)号：US5293596A

公开(公告)日：1994-03-08

申请号：US658154

申请日：1991-02-20

Applicant: Masaki Toyokura ,  Kunitoshi Aono ,  Toshiyuki Araki

Inventor： Masaki Toyokura ,  Kunitoshi Aono ,  Toshiyuki Araki

IPC: G06F12/02 ,  G06F12/00

CPC classification number: G06F12/0207

Abstract: A multidimensional address generator for generating one-dimensional addresses respectively corresponding to P.sub.1 .times.P.sub.2 .times. . . . .times.P.sub.N data of a predetermined region of an N-dimensional entire data array (N is a positive integer larger than one) which has Q.sub.1 .times.Q.sub.2 .times. . . . .times.Q.sub.N data (P.sub.1, . . . and P.sub.N and Q.sub.1, . . . and Q.sub.N are positive integers and P.sub.1 .ltoreq.Q.sub.1, . . . and P.sub.N .ltoreq.Q.sub.N). The generator comprises a first to third multiplexers, an adder and a first to Nth accumulating registers. In the generator, the first multiplexer selects one of a first to Nth increments respectively corresponding to a first to Nth directions, in which data to successively be accessed are arranged. Further, the second multiplexer selects one of data stored in the first to Nth accumulating registers, and the third multiplexer selects between the start address and an output of the adder. Moreover, data selected by the first multiplexer is added by the adder to data selected by the second multiplexer, and data selected by the third multiplexer is inputted to the first to Nth accumulating registers. Furthermore, a start address is written to the first to Nth accumulating registers when the address generator is activated. Moreover, the first increment is added to the data held in the first accumulating register in each of Cycles 1 to (P.sub.1 -1) and . . . and Cycles (P.sub.N P.sub.N-1 . . . P.sub.2 -1)P.sub.1 +1 to (P.sub.N P.sub.N-1 . . . P.sub.2 P.sub.1 -1), the first increment is added to the data held in the first accumulating register, and a result is written thereto. Additionally, an nth increment (n=2, 3, . . . , N) is added to the data held in the nth accumulating register, and a result is written to the first to nth accumulating registers, every P.sub.n-1 P.sub.n-2 . . . P.sub.1 cycles during Cycles P.sub.n P.sub.n-1 P.sub.n-2 . . . P.sub.1 to (P.sub.n -1)P.sub.n-1 P.sub.n-2 . . . P.sub.1 and so on. The data finally obtained in the first accumulating register is outputted. Consequently, an operation of accessing a plurality of multidimensional data can be performed easily and quickly.

公开(公告)号：US4791677A

公开(公告)日：1988-12-13

申请号：US941625

申请日：1986-12-11

Applicant: Toshiki Mori ,  Haruyasu Yamada ,  Kunitoshi Aono ,  Masakatsu Maruyama

Inventor： Toshiki Mori ,  Haruyasu Yamada ,  Kunitoshi Aono ,  Masakatsu Maruyama

IPC: G06T5/20 ,  G06K9/36 ,  G06F15/336 ,  G06K9/64

CPC classification number: G06T5/20

Abstract: An image signal processor which includes a local image register for receiving local image area data of m rows.times.n columns pixels, and a expansion use register of m row.times.l column pixels coupled to the output of the local image register. Thereby, expansion of local image area, and parallel processing can be readily conducted.

Abstract translation: 一种图像信号处理器，包括用于接收m行×x列像素的本地图像区域数据的本地图像寄存器和耦合到本地图像寄存器的输出的m行x1列像素的扩展使用寄存器。 因此，可以容易地进行局部图像区域的扩展和并行处理。

公开(公告)号：US08125817B2

公开(公告)日：2012-02-28

申请号：US12867392

申请日：2009-12-16

Applicant: Takeshi Takagi ,  Shunsaku Muraoka ,  Ryotaro Azuma ,  Kunitoshi Aono

Inventor： Takeshi Takagi ,  Shunsaku Muraoka ,  Ryotaro Azuma ,  Kunitoshi Aono

IPC: G11C11/00 ,  G11C5/06 ,  G11C11/34 ,  G11C5/14 ,  G11C7/00

CPC classification number: H01L27/101 ,  G11C13/0002 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1675

Abstract: To provide a nonvolatile storage device (100) which is capable of achieving stable operation and includes variable resistance elements. The nonvolatile storage device (100) includes: memory cells (M111, M112, . . .) each of which is provided at three-dimensional cross-points between word lines (WL0, WL1, . . .) and bit lines (BL0, BL1, . . .) and having a resistance value that reversibly changes based on an electrical signal; a row selection circuit-and-driver (103) provided with transistors (103a) each of which applies a predetermined voltage to a corresponding one of the word lines (WL0, WL1, . . .); a column selection circuit-and-driver (104) provided with transistors (104a) each of which applies a predetermined voltage to a corresponding one of the bit lines (BL0, BL1, . . .); and a substrate bias circuit (110) which applies a forward bias voltage to a substrate of such transistors (103a and 104a).

Abstract translation: 提供能够实现稳定操作并且包括可变电阻元件的非易失性存储装置（100）。 非易失性存储装置（100）包括：存储单元（M111，M112 ...），每个存储单元设置在字线（WL0，WL1 ...）与位线（BL0， BL1，...），并且具有基于电信号可逆地改变的电阻值; 具有晶体管（103a）的行选择电路驱动器（103），每个晶体管将预定电压施加到对应的一个字线（WL0，WL1 ...）; 具有晶体管（104a）的列选择电路驱动器（104），每个晶体管将预定电压施加到相应的位线（BL0，BL1 ...）中; 以及向这种晶体管（103a和104a）的衬底施加正向偏置电压的衬底偏置电路（110）。

公开(公告)号：US06570231B1

公开(公告)日：2003-05-27

申请号：US09652989

申请日：2000-08-31

Applicant: Masahiro Yasumi ,  Ichirou Matsuo ,  Toshiki Yabu ,  Mizuki Segawa ,  Kunitoshi Aono ,  Akihiko Ohtani ,  Takayuki Minemaru ,  Tadashi Fukumoto

Inventor： Masahiro Yasumi ,  Ichirou Matsuo ,  Toshiki Yabu ,  Mizuki Segawa ,  Kunitoshi Aono ,  Akihiko Ohtani ,  Takayuki Minemaru ,  Tadashi Fukumoto

IPC: H01L2976

CPC classification number: H01L21/823842 ,  H01L21/823835 ,  H01L21/823871

Abstract: An n-channel active region, a p-channel active region and an isolation insulating film are formed, and a silicon film is deposited via a gate insulating film. After introducing n-type impurities into the n-channel region and p-type impurities into the p-channel region, a silicon gate electrode is formed in such a manner that its width is enlarged only in the boundary portion between the n-channel region and the p-channel region. After forming a side wall insulating film, an n-channel diffusion layer and a p-channel diffusion layer, a metal silicide layer is formed in a self-aligned manner on the surfaces of the silicon gate electrode, the n-channel diffusion layer and the p-channel diffusion layer.

Abstract translation: 形成n沟道有源区，p沟道有源区和隔离绝缘膜，通过栅极绝缘膜沉积硅膜。 在n沟道区域中引入n型杂质并将p型杂质引入p沟道区中后，形成硅栅电极，使其宽度仅在n沟道区域之间的边界部分扩大 和p沟道区域。 在形成侧壁绝缘膜，n沟道扩散层和p沟道扩散层之后，在硅栅极，n沟道扩散层和n沟道扩散层的表面上以自对准的方式形成金属硅化物层 p沟道扩散层。

公开(公告)号：US5517666A

公开(公告)日：1996-05-14

申请号：US185367

申请日：1994-01-24

Applicant: Akihiko Ohtani ,  Toshiyuki Araki ,  Kunitoshi Aono ,  Toshihide Akiyama

Inventor： Akihiko Ohtani ,  Toshiyuki Araki ,  Kunitoshi Aono ,  Toshihide Akiyama

IPC: G06F15/80 ,  G06F15/347

CPC classification number: G06F15/8092

Abstract: A program controlled processor comprises a scalar processing unit 101 for normal data (=scalar) operations and branch processing, a plurality of vector processing units 102 of identical structure, a vector distributor 103 for distributing input data as block vectors to vector memory 304 in each vector processing unit 102, a vector coupler 104 for coupling the block vectors stored in vector memory 404 in each vector processing unit 102 to provide output vectors, an instruction memory 105 for storing the operations of these circuit blocks as an operating program, a sequencer 106 for sequentially reading the instruction memory 105, and a decoder 107 for interpreting the read instructions and outputting a control signal to each circuit block. The scalar processing unit 101 comprises a scalar bus input enabling the scalar processing unit 101 to refer scalar registers in the vector processing units 102. The program controlled processor has improved data processing performance because parallel vector instructions are operated in parallel in the vector processing units of block data distributed by the vector distributor.

Abstract translation: 程序控制处理器包括用于正常数据（=标量）操作和分支处理的标量处理单元101，具有相同结构的多个向量处理单元102，用于将输入数据作为块向量分配给每个矢量存储器304的向量分配器103 矢量处理单元102，用于将存储在矢量存储器404中的块矢量耦合到每个矢量处理单元102中以提供输出矢量的矢量耦合器104，用于存储作为操作程序的这些电路块的操作的指令存储器105，定序器106 用于顺序读取指令存储器105，以及解码器107，用于解读读取指令并向每个电路块输出控制信号。 标量处理单元101包括标量总线输入，使得标量处理单元101能够引用矢量处理单元102中的标量寄存器。程序控制处理器具有改进的数据处理性能，因为并行矢量指令在矢量处理单元中并行操作 由矢量分配器分发的块数据。

公开(公告)号：US5278781A

公开(公告)日：1994-01-11

申请号：US51273

申请日：1993-04-23

Applicant: Kunitoshi Aono ,  Masaki Toyokura ,  Shiro Sakiyama ,  Toshiyuki Araki ,  Masakatsu Maruyama

Inventor： Kunitoshi Aono ,  Masaki Toyokura ,  Shiro Sakiyama ,  Toshiyuki Araki ,  Masakatsu Maruyama

IPC: G06F7/544 ,  G06F17/10 ,  G06F7/38

CPC classification number: G06F7/5443 ,  G06F17/10 ,  G06F2207/3884

Abstract: A digital signal processing system includes a plurality of multiplier/accumulators for executing a pipeline processing operation. Each of the plurality of multiplier/accumulators includes a multiplication part and an addition part. The multiplication parts includes N pipeline registers for storing N intermediate outputs of a multiplier. The addition part includes a Wallace tree transformation unit for transforming a sum of N+1 inputs into two transformation outputs, and an adder for adding the two transformation outputs. The N+1 inputs includes the N intermediate outputs from the multiplication part and the one addition output from the adder.

Abstract translation: 数字信号处理系统包括用于执行流水线处理操作的多个乘法器/累加器。 多个乘法器/累加器中的每一个包括乘法部分和加法部分。 乘法部分包括用于存储乘法器的N个中间输出的N个流水线寄存器。 加法部分包括用于将N + 1个输入的和转换为两个变换输出的华莱士树变换单元和用于将两个变换输出相加的加法器。 N + 1输入包括来自乘法部分的N个中间输出和来自加法器的一个相加输出。