公开(公告)号：US20130080741A1

公开(公告)日：2013-03-28

申请号：US13246184

申请日：2011-09-27

申请人： Alexander Rabinovitch ,  Leonid Dubrovin ,  Amichay Amitay

发明人： Alexander Rabinovitch ,  Leonid Dubrovin ,  Amichay Amitay

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/325 ,  G06F9/3867 ,  G06F9/3877

摘要： An apparatus generally having a first circuit, a second circuit and a third circuit is disclosed. The first circuit may have a counter and may be configured to adjust at least one control signal in response to a current value of the counter. The first circuit may be implemented only in hardware. The counter generally counts a number of loops in which a plurality of instructions are executed. The second circuit may be configured to set the counter to an initial value. The third circuit may be configured to execute the instructions using a plurality of data items as a plurality of operands such that at least two of the instructions use different ones of the operands. The data items may be routed to the third circuit in response to the control signal. The apparatus generally forms a processor.

摘要翻译： 公开了一种通常具有第一电路，第二电路和第三电路的装置。 第一电路可以具有计数器并且可以被配置为响应于计数器的当前值来调整至少一个控制信号。 第一电路可以仅在硬件中实现。 该计数器通常对执行多个指令的循环进行计数。 第二电路可以被配置为将计数器设置为初始值。 第三电路可以被配置为使用多个数据项作为多个操作数来执行指令，使得至少两个指令使用不同的操作数。 数据项可以响应于控制信号被路由到第三电路。 该装置通常形成处理器。

公开(公告)号：US20130046961A1

公开(公告)日：2013-02-21

申请号：US13209681

申请日：2011-08-15

申请人： Alexander Rabinovitch ,  Leonid Dubrovin ,  Eran Dosh ,  Noam Abda ,  Vered Antebi

发明人： Alexander Rabinovitch ,  Leonid Dubrovin ,  Eran Dosh ,  Noam Abda ,  Vered Antebi

IPC分类号： G06F9/38

CPC分类号： G06F9/30072 ,  G06F9/30094 ,  G06F9/3842

摘要： An apparatus generally having an interface circuit and a processor. The interface circuit may have a queue and a connection to a memory. The processor may have a pipeline. The processor is generally configured to (i) place an address in the queue in response to processing a first instruction in a first stage of the pipeline, (ii) generate a flag by processing a second instruction in a second stage of the pipeline, the second instruction may be processed in the second stage after the first instruction is processed in the first stage, and (iii) generate a signal based on the flag in a third stage of the pipeline. The third stage may be situated in the pipeline after the second stage. The interface circuit is generally configured to cancel the address from the queue without transferring the address to the memory in response to the signal having a disabled value.

摘要翻译： 通常具有接口电路和处理器的装置。 接口电路可以具有队列和到存储器的连接。 处理器可能具有管道。 处理器通常被配置为（i）响应于处理流水线的第一级中的第一指令而将地址放置在队列中，（ii）通过在流水线的第二级中处理第二指令来生成标志， 可以在第一阶段处理第一指令之后的第二阶段中处理第二指令，以及（iii）基于流水线的第三级中的标志生成信号。 第三阶段可以在第二阶段之后的管道中。 接口电路通常被配置为响应于具有禁用值的信号，从队列中取消地址而不将地址传送到存储器。

公开(公告)号：US20120151150A1

公开(公告)日：2012-06-14

申请号：US12965136

申请日：2010-12-10

申请人： Alexander Rabinovitch ,  Leonid Dubrovin

发明人： Alexander Rabinovitch ,  Leonid Dubrovin

IPC分类号： G06F12/08

CPC分类号： G06F12/0862 ,  G06F9/3455 ,  G06F9/355 ,  G06F9/383 ,  Y02D10/13

摘要： A method is provided for performing cache line fetching and/or cache fetch ahead in a processing system including at least one processor core and at least one data cache operatively coupled with the processor. The method includes the steps of: retrieving post modification information from the processor core and a memory address corresponding thereto; and the processing system performing, as a function of the post modification information and the memory address retrieved from the processor core, cache line fetching and/or cache fetch ahead control in the processing system.

摘要翻译： 提供了一种用于在包括至少一个处理器核心和与处理器可操作地耦合的至少一个数据高速缓存的处理系统中执行高速缓存行提取和/或高速缓存提取的方法。 该方法包括以下步骤：从处理器核心检索后修改信息和与之对应的存储器地址; 并且所述处理系统根据所述后修改信息和从所述处理器核心检索的所述存储器地址执行所述处理系统中的高速缓存行提取和/或高速缓存提取控制。

公开(公告)号：US20120151149A1

公开(公告)日：2012-06-14

申请号：US12967155

申请日：2010-12-14

申请人： Leonid Dubrovin ,  Alexander Rabinovitch

发明人： Leonid Dubrovin ,  Alexander Rabinovitch

IPC分类号： G06F12/08

CPC分类号： G06F12/0862 ,  G06F12/126

摘要： A method is provided for performing caching in a processing system including at least one data cache. The method includes the steps of: determining whether each of at least a subset of cache entries stored in the data cache comprises data that has been loaded using fetch ahead (FA); associating an identifier with each cache entry in the subset of cache entries, the identifier indicating whether the cache entry comprises data that has been loaded using FA; and implementing a cache replacement policy for controlling replacement of at least a given cache entry in the data cache with a new cache entry as a function of the identifier associated with the given cache entry.

摘要翻译： 提供了一种用于在包括至少一个数据高速缓存的处理系统中执行高速缓存的方法。 该方法包括以下步骤：确定存储在数据高速缓冲存储器中的至少一个高速缓存条目子集中的每一个是否包含使用提前（FA）加载的数据; 将标识符与高速缓存条目子集中的每个高速缓存条目相关联，所述标识符指示高速缓存条目是否包括已经使用FA加载的数据; 以及实施高速缓存替换策略，用于根据与所述给定高速缓存条目相关联的标识符来控制用新的高​​速缓存条目来替换所述数据高速缓存中的至少一个给定高速缓存条目。

公开(公告)号：US08171269B2

公开(公告)日：2012-05-01

申请号：US12399622

申请日：2009-03-06

申请人： Alexander Rabinovitch ,  Leonid Dubrovin

发明人： Alexander Rabinovitch ,  Leonid Dubrovin

IPC分类号： G06F9/38

CPC分类号： G06F9/3844 ,  G06F9/3806

摘要： Various embodiments of the present invention provide systems and methods for branch prediction. As an example, some embodiments of the present invention provides processor circuits that include a program address circuit, a branch target buffer, a branch prediction replacement circuit, and an execution pipeline. The branch target buffer includes a plurality of entries each associated with a respective change of flow instruction. Each entry includes an indication of an entry source and a next program address corresponding to the respective change of flow instruction. The branch prediction replacement circuit is operable to determine replacement priorities of the plurality of entries based at least in part on the entry source for each of the plurality of entries. The execution pipeline receives an executable instruction corresponding to one of the next program addresses.

摘要翻译： 本发明的各种实施例提供了用于分支预测的系统和方法。 作为示例，本发明的一些实施例提供了包括程序地址电路，分支目标缓冲器，分支预测替换电路和执行流水线的处理器电路。 分支目标缓冲器包括多个条目，每个条目与相应的流程指令改变相关联。 每个条目包括与流程指令的相应改变对应的入口源和下一个程序地址的指示。 分支预测替换电路可操作以至少部分地基于多个条目中的每一个的入口源来确定多个条目的替换优先级。 执行流水线接收与下一个程序地址之一相对应的可执行指令。

公开(公告)号：US20100293304A1

公开(公告)日：2010-11-18

申请号：US12467228

申请日：2009-05-15

申请人： Nimrod Alexandron ,  Alexander Rabinovitch ,  Leonid Dubrovin

发明人： Nimrod Alexandron ,  Alexander Rabinovitch ,  Leonid Dubrovin

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： A DMA controller and a method for statistical allocation of multichannel DMA bandwidth. In one embodiment, the DMA controller includes: (1) channel interfaces including respective counters and configured to provide request signals, priority signals and counter value signals representing current values of the counters at a given time and (2) a grant control unit coupled to the channel interfaces and configured to grant DMA access to one of the channel interfaces based on values of the priority signals and the counter value signals.

摘要翻译： DMA控制器和多通道DMA带宽的统计分配方法。 在一个实施例中，DMA控制器包括：（1）包括相应计数器的通道接口，并且被配置为在给定时间提供表示计数器的当前值的请求信号，优先级信号和计数器值信号，以及（2）耦合到 信道接口并且被配置为基于优先级信号和计数器值信号的值来授予对其中一个信道接口的DMA访问。

公开(公告)号：US08892621B2

公开(公告)日：2014-11-18

申请号：US13330436

申请日：2011-12-19

申请人： Leonid Dubrovin ,  Alexander Rabinovitch

发明人： Leonid Dubrovin ,  Alexander Rabinovitch

IPC分类号： G06F7/533

CPC分类号： G06F7/5336

摘要： A multiplier circuit for generating a product of at least first and second multiplicands includes encoding circuitry comprising a plurality of encoders. Each of the encoders is operative to receive at least a subset of bits of the first multiplicand and to generate a partial product corresponding to the subset of bits of the first multiplicand. The encoding circuitry is further operative to incorporate a negation of the product as a function of at least a first control signal supplied to the multiplier circuit. The multiplier circuit further includes summation circuitry coupled with the encoding circuitry. The summation circuitry is operative to sum each of the partial products generated by the encoding circuitry to thereby generate the product without performing post-incrementation.

摘要翻译： 用于产生至少第一和第二被乘数的乘积的乘法器电路包括包括多个编码器的编码电路。 每个编码器操作以接收第一被乘数的比特的至少一个子集，并且生成对应于第一被乘数的比特的子集的部分乘积。 编码电路还可操作以将产品的否定作为至少提供给乘法器电路的第一控制信号的函数。 乘法器电路还包括与编码电路耦合的求和电路。 求和电路用于对由编码电路产生的每个部分乘积进行求和，从而生成产品而不执行后递增。

公开(公告)号：US08880815B2

公开(公告)日：2014-11-04

申请号：US13400212

申请日：2012-02-20

申请人： Nimrod Alexandron ,  Alexander Rabinovitch ,  Leonid Dubrovin

发明人： Nimrod Alexandron ,  Alexander Rabinovitch ,  Leonid Dubrovin

IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F12/06

CPC分类号： G06F12/02 ,  G06F9/3013 ,  G06F9/3555 ,  G06F12/06

摘要： An apparatus having a memory and a controller is disclosed. The controller may be configured to (i) receive a read request from a processor, the read request comprising a first value and a second value, (ii) where the read request is an indirect memory access, (a) generate a first address in response to the first value, (b) read data stored in the memory at the first address and (c) generate a second address in response to the second value and the data, (iii) where the read request is a direct memory access, generate the second address in response to the second value and (iv) read a requested data stored in the memory at the second address.

摘要翻译： 公开了一种具有存储器和控制器的装置。 控制器可以被配置为（i）从处理器接收读取请求，所述读取请求包括第一值和第二值，（ii）其中所述读取请求是间接存储器访问，（a）生成第一地址 响应于第一值，（b）读取存储在第一地址的存储器中的数据，（c）响应于第二值和数据产生第二地址，（iii）读取请求是直接存储器存取， 响应于第二值产生第二地址，以及（iv）在第二地址处读取存储在存储器中的请求数据。

公开(公告)号：US20130318307A1

公开(公告)日：2013-11-28

申请号：US13478561

申请日：2012-05-23

申请人： Alexander Rabinovitch ,  Leonid Dubrovin ,  Vladimir Kopilevitch

发明人： Alexander Rabinovitch ,  Leonid Dubrovin ,  Vladimir Kopilevitch

IPC分类号： G06F12/08

CPC分类号： G06F12/0862

摘要： An apparatus including a tag comparison logic and a fetch-ahead generation logic. The tag comparison logic may be configured to present a miss address in response to detecting a cache miss. The fetch-ahead generation logic may be configured to select between a plurality of predefined fetch ahead policies in response to a memory access request and generate one or more fetch addresses based upon the miss address and a selected fetch ahead policy.

摘要翻译： 一种包括标签比较逻辑和提前生成逻辑的装置。 标签比较逻辑可以被配置为响应于检测到高速缓存未命中而呈现未命中地址。 提前生成逻辑可以被配置为响应于存储器访问请求在多个预定义的提前提前策略之间进行选择，并且基于未命中的地址和所选择的前进提前策略生成一个或多个提取地址。

公开(公告)号：US20130282780A1

公开(公告)日：2013-10-24

申请号：US13453056

申请日：2012-04-23

申请人： Leonid Dubrovin ,  Alexander Rabinovitch

发明人： Leonid Dubrovin ,  Alexander Rabinovitch

IPC分类号： G06F7/485

CPC分类号： G06F7/485

摘要： A method of subtracting floating-point numbers includes determining whether a first sign associated with a first floating-point number is unequal to a second sign associated with a second floating-point number, determining whether a first exponent associated with the first floating-point number is less than a second exponent associated with the second floating-point number, negating a first mantissa associated with the first floating-point number when the first sign is unequal to the second sign and determining that the first exponent is less than the second exponent, and adding the first mantissa to a second mantissa associated with the second floating-point number when the first sign is unequal to the second sign and determining that the first exponent is less than the second exponent. Embodiments of a corresponding computer-readable medium and device are also provided.

摘要翻译： 减去浮点数的方法包括确定与第一浮点数相关联的第一符号是否不等于与第二浮点数相关联的第二符号，确定是否与第一浮点数相关联的第一指数 小于与第二浮点数相关联的第二指数，当第一符号不等于第二符号并且确定第一指数小于第二指数时，否定与第一浮点数相关联的第一尾数， 以及当所述第一符号不等于所述第二符号并且确定所述第一指数小于所述第二指数时，将所述第一尾数添加到与所述第二浮点数相关联的第二尾数。 还提供了相应的计算机可读介质和设备的实施例。