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公开(公告)号：US5142494A
公开(公告)日：1992-08-25
申请号：US692797
申请日：1991-04-29
申请人： Lionel J. D'Luna
发明人： Lionel J. D'Luna
摘要： A digital line delay architecture is provided that requires a minimum of chip space, has low power requirements, is variable or programmable in length, and is flexible to permit changes in aspect ratio. The digital line delay architecture is self-multiplexing and therefore requires no external addressing for the multiplexing function, and is particularly suited for use as a video line delay in a single chip digital image processing device. In particular, a pointer unit is employed to sequentially address a plurality of word storage locations provided in a storage unit. The pointer unit includes a number of shift-registers that sqeuentially shift a logic "1" along the length of the pointer unit to accomplish the addressing.
摘要翻译： 提供了一种数字线路延迟架构，其需要最小的芯片空间，具有低功率需求，可变长度或可编程长度，并且是灵活的，以允许更改纵横比。 数字线路延迟架构是自复用的，因此不需要用于复用功能的外部寻址，并且特别适合用作单芯片数字图像处理设备中的视频行延迟。 特别地，使用指针单元来顺序地寻址提供在存储单元中的多个字存储位置。 指针单元包括多个移位寄存器，其沿着指针单元的长度平移地移动逻辑“1”以完成寻址。
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公开(公告)号：US5042007A
公开(公告)日：1991-08-20
申请号：US488822
申请日：1990-02-26
申请人： Lionel J. D'Luna
发明人： Lionel J. D'Luna
CPC分类号： G06F7/785
摘要： A digital storage device is provided that includes a storage unit having a plurality of word storage locations, each of the word storage locations being coupled to a corresponding read enable line and write enable line, and a pointer unit for addressing the read enable lines and the write enable lines to permit data to be written into the word storage locations in a first sequence in a first operating mode and to be retrieved from the word storage locations in a second sequence that is transposed from the first sequence in a second operating mode; and a clock generator coupled to the pointer unit which controls the operation of the pointer unit.
摘要翻译： 提供一种数字存储设备，其包括具有多个字存储位置的存储单元，每个字存储位置耦合到相应的读使能线和写使能线，以及指针单元，用于寻址读使能线和 写入使能线，以允许以第一操作模式以第一序列将数据写入字存储位置，并且以第二操作模式从第一序列转置的第二序列中的字存储位置检索; 以及耦合到指针单元的时钟发生器，其控制指针单元的操作。
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13.发明授权Detail processing method and apparatus providing uniform processing of horizontal and vertical detail components 失效详细的处理方法和装置提供水平和垂直细节部件的统一处理
公开(公告)号：US4962419A
公开(公告)日：1990-10-09
申请号：US310456
申请日：1989-02-13
CPC分类号： H04N9/646
摘要： In a signal processing network including a color correction matrix and gamma compensation, detail processing is disclosed that includes a detail extraction circuit for generating a detail signal from an un-matrixed green signal and a detail enhancement circuit for adding the detail signal to the matrixed, gamma-corrected red, green and blue signals. The un-matrixed green signal is converted to a gamma-corrected green signal and separately input to vertical and horizontal high pass filters, which separate detail components representative of vertical and horizontal detail, respectively. The vertical detail is additionally input to a horizontal low pass filter to eliminate excessive enhancement of diagonal image components. The detail components are cored and input to the detail enhancement circuit. As a result of bypassing the color correction matrix and inserting the modified detail, including the diminished diagonal contribution, into the signal channel after gamma correction, the various detail components receive a substantially uniform visual enhancement regardless of orientation or density in the image.
摘要翻译： 在包括颜色校正矩阵和伽马补偿的信号处理网络中，公开了包括用于从非矩阵绿色信号生成细节信号的细节提取电路和用于将细节信号加到矩阵化的细节增强电路的细节处理， 伽马校正的红，绿和蓝信号。 未矩阵化的绿色信号被转换为伽马校正的绿色信号，并分别输入到垂直和水平高通滤波器，分别分别表示垂直和水平细节的细节分量。 垂直细节另外输入到水平低通滤波器以消除对角图像分量的过度增强。 细节部件是细节增强电路的核心和输入。 由于绕过颜色校正矩阵并将经修改的细节（包括减小的对角线贡献）插入到伽马校正之后的信号通道中，各种细节分量接收基本均匀的视觉增强，而与图像中的取向或密度无关。
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14.发明申请Method and System for Receiving Audio, Video and Data Services with ATSC Enabled Television Sets 审中-公开用于接收具有ATSC使能电视机的音频，视频和数据业务的方法和系统公开(公告)号：US20080304596A1
公开(公告)日：2008-12-11
申请号：US11761504
申请日：2007-06-12
申请人： Loke Tan , Lionel J. D'Luna , Robindra Joshi
发明人： Loke Tan , Lionel J. D'Luna , Robindra Joshi
IPC分类号： H03D1/24
CPC分类号： H04N21/4344 , H04N21/4382
摘要： Certain aspects of a method and system for receiving audio, video and data services with advanced television systems committee (ATSC) enabled television sets may be provided. Aspects of the method may include conversion of a plurality of received quadrature amplitude modulated (QAM) signals into a plurality of vestigial side band (VSB) signals within a set-top box. The set top box may tune to each of the plurality of received QAM signals and demodulate each of the plurality of received QAM signals into a plurality of bitstreams and demultiplex the plurality of bitstreams. The demultiplexed plurality of bitstreams may be modulated into a plurality of VSB signals. The plurality of VSB signals may be modulated into a plurality of RF signals. One or more of the plurality of RF signals may be communicated to at least one of a plurality of VSB enabled television sets.
摘要翻译： 可以提供用于接收具有高级电视系统委员会（ATSC）的电视机的音频，视频和数据服务的方法和系统的某些方面。 该方法的方面可以包括将多个接收的正交幅度调制（QAM）信号转换成机顶盒内的多个残留边带（VSB）信号。 机顶盒可以调谐到多个接收到的QAM信号中的每一个，并且将多个接收的QAM信号中的每一个解调为多个比特流并对多个比特流进行解复用。 解复用的多个比特流可以被调制成多个VSB信号。 多个VSB信号可以被调制成多个RF信号。 多个RF信号中的一个或多个可以被传送到多个启用VSB的电视机中的至少一个。
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15.发明授权
公开(公告)号：US5809182A
公开(公告)日：1998-09-15
申请号：US697388
申请日：1996-08-23
CPC分类号： G06T3/4007 , H04N19/63 , H04N19/42
摘要： A resampling application specific integrated circuit (RSA) supports image interpolation or decimation by any arbitrary factor in order to provide flexibility, and utilizes a neighborhood of up to 9.times.9 pixels to produce image data of high quality. The RSA contains a separate vertical and horizontal filter units for vertical resizing and horizontal resizing operations, vertical and horizontal position accumulator units, a configuration register unit for loading the vertical and horizontal position accumulator units, and a memory management unit to interface the RSA to external memory banks. The vertical and horizontal filter units contain nine multipliers and nine corresponding coefficient memories, with each memory preferably containing storage space for thirty-two coefficients. The coefficients are addressed on a pixel by pixel basis in response to the outputs of the vertical and horizontal position accumulator units. The RSA is designed to handle an input data stream that contains multiple color components and simultaneously resizes all of the color components.
摘要翻译： 重采样应用专用集成电路（RSA）通过任意因素支持图像插值或抽取，以提供灵活性，并利用高达9x9像素的邻域产生高质量的图像数据。 RSA包含用于垂直调整大小和水平调整大小操作的单独的垂直和水平滤波器单元，垂直和水平位置累加器单元，用于加载垂直和水平位置累加器单元的配置寄存器单元，以及用于将RSA接口到外部的存储器管理单元 记忆库。 垂直和水平滤波器单元包含九个乘法器和九个对应的系数存储器，每个存储器优选地包含用于三十二个系数的存储空间。 响应于垂直和水平位置累加器单元的输出，逐个地逐个地对系数进行寻址。 RSA设计用于处理包含多个颜色分量并同时调整所有颜色分量的输入数据流。
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16.发明授权Method and apparatus for compensating for sensitivity variations in the output of a solid state image sensor 失效用于补偿固态图像传感器输出的灵敏度变化的方法和装置
公开(公告)号：US5086343A
公开(公告)日：1992-02-04
申请号：US522334
申请日：1990-05-11
CPC分类号： H04N1/401 , H04N5/2176
摘要： A correction circuit processes digitized signals from an image sensor and generates gain correction values to compensate for variations in the output of the sensor. While imaging a gain calibration object, the sensor is operated in a calibration mode in which a plurality of calibration values are generated that pertain to each photosite. The digitized calibration values are transformed into log space for processing by a gain level averaging circuit. The log calibration signals are first subtracted from a reference corresponding to a maximum expected signal value. The difference signals are serially accumulated by means of pair of registers and an adder, and the sum is stored in a gain memory. In a subsequent normal operating mode, the summed signals for each photosite are retrieved from the gain memory and bit-shifted to form an average correction value for each photosite. The correction values are applied to an adder in synchronism with sensor signals from like photosites and added therewith in log space to provide gain compensation.
摘要翻译： 校正电路处理来自图像传感器的数字化信号，并且生成增益校正值以补偿传感器的输出的变化。 在对增益校准对象进行成像时，传感器在校准模式下操作，其中生成与每个光子相关的多个校准值。 数字化校准值被变换为对数空间，以便通过增益电平平均电路进行处理。 首先从对应于最大预期信号值的参考中减去对数校准信号。 差分信号通过一对寄存器和一个加法器串行累加，并且该和存储在增益存储器中。 在随后的正常操作模式中，从增益存储器检索每个光子的加和信号并进行位移以形成每个光子的平均校正值。 校正值与来自类似照相机的传感器信号同步地应用于加法器，并将其与对数空间相加，以提供增益补偿。
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公开(公告)号：US5008563A
公开(公告)日：1991-04-16
申请号：US402585
申请日：1989-09-05
CPC分类号： H04N5/2173 , H03K3/033 , H03K5/133 , H03K2005/00195
摘要： A clock generator for producing a pulse that can be adjusted in width and position. The positive edge of an incoming clock signal is slowed by an adjustable rise time inverter with a selected bias voltage until a selected threshold voltage level is met by a Schmitt trigger. The output from the Schmitt trigger is directed through a similar delay circuit to establish the pulse width of the pulse.
摘要翻译： 用于产生可以在宽度和位置上调节的脉冲的时钟发生器。 输入时钟信号的上升沿由具有选定偏置电压的可调节上升时间反相器减慢，直到施密特触发器满足选定的阈值电压电平。 来自施密特触发器的输出通过类似的延迟电路被引导以建立脉冲的脉冲宽度。
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18.发明授权Image processor with input buffering to multiple digital signal processors 失效具有输入缓冲的多个数字信号处理器的图像处理器
公开(公告)号：US5523788A
公开(公告)日：1996-06-04
申请号：US313632
申请日：1994-09-27
申请人： Ram Kannegundla , Lionel J. D'Luna , Yung-Rai Lee
发明人： Ram Kannegundla , Lionel J. D'Luna , Yung-Rai Lee
摘要： A system architecture is provided that includes an image sensor unit operable in a single channel mode and a dual channel mode. The image sensor unit includes an electronic image sensor comprising a row and column array of pixel elements, wherein the rows of the array having a line length of N pixels. First and second digital signal processing units for processing image data generated by the image sensor unit into color component image data are provided, wherein each of said first and second digital signal processing units has a line length processing capacity less than N pixels. An input buffer, coupled between outputs of the image sensor unit and inputs to the digital signal processing units, simultaneously receives two lines of image data from the image sensor unit in the dual channel mode of operation, and sequentially supplies a first portion of each of the simultaneously received image lines to the first digital signal processing unit and a second portion of each of the simultaneously received image lines to the second digital signal processing unit. An output buffer, coupled to the output of the first and second digital signal processing units, combines the color component image data generated by the first and second digital signal processing units into color component image lines of length N pixels. A control unit controls the operation of the image sensor unit, the input buffer, the first and second digital signal processing units, and the output buffer. A frame store receives and stores the color component image lines generated by the output buffer, and a monitor displays the image lines at a frame rate that is about twice the operating frame rate of the image sensor unit.
摘要翻译： 提供了一种系统架构，其包括可在单通道模式和双通道模式下操作的图像传感器单元。 图像传感器单元包括电子图像传感器，其包括像素元件的行和列阵列，其中阵列的行具有N个像素的线长度。 提供了用于将由图像传感器单元生成的图像数据处理为彩色分量图像数据的第一和第二数字信号处理单元，其中所述第一和第二数字信号处理单元中的每一个具有小于N个像素的行长处理能力。 耦合到图像传感器单元的输出和数字信号处理单元的输入之间的输入缓冲器在双通道操作模式中同时从图像传感器单元接收两行图像数据，并且顺序地将第一部分的 同时接收到的图像行到第一数字信号处理单元和每个同时接收的图像行的第二部分到第二数字信号处理单元。 耦合到第一和第二数字信号处理单元的输出的输出缓冲器将由第一和第二数字信号处理单元生成的颜色分量图像数据组合成长度为N个像素的颜色分量图像行。 控制单元控制图像传感器单元，输入缓冲器，第一和第二数字信号处理单元以及输出缓冲器的操作。 帧存储器接收并存储由输出缓冲器生成的颜色分量图像线，并且监视器以大约是图像传感器单元的操作帧速率的两倍的帧速率显示图像行。
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19.发明授权Selectively configurable integrated circuit device for performing multiple digital signal processing functions 失效可选配置的集成电路设备，用于执行多个数字信号处理功能
公开(公告)号：US5311459A
公开(公告)日：1994-05-10
申请号：US946124
申请日：1992-09-17
CPC分类号： G06F17/16
摘要： A single integrated circuit device is disclosed that is capable of selectively functioning in real time as either a sequential matrix multiplier, a parallel matrix multiplier, a convolver or a finite input response FIR filter in order to process image data. A core group of multipliers is used to provide the basic multiplication operation that is common to each of the desired image processing functions. Input data router unit, coefficient router units and an output data router unit are responsive to mode selection control signals, supplied to a mode selection port, to route the appropriate input data and coefficients to the core group of multipliers and to route the output of the adders to the correct output port(s) for each of the desired processing functions.
摘要翻译： 公开了能够作为顺序矩阵乘法器，并行矩阵乘法器，卷积器或有限输入响应FIR滤波器实时选择性地运行以便处理图像数据的单个集成电路器件。 使用核心的乘法器组来提供每个所需图像处理功能共同的基本乘法运算。 输入数据路由器单元，系数路由器单元和输出数据路由器单元响应于提供给模式选择端口的模式选择控制信号，以将适当的输入数据和系数路由到乘法器的核心组，并且路由输出 为每个所需的处理功能添加到正确的输出端口。
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20.发明授权Digital correlated double sampling circuit for sampling the output of an image sensor 失效数字相关双采样电路，用于采集图像传感器的输出
公开(公告)号：US5086344A
公开(公告)日：1992-02-04
申请号：US522030
申请日：1990-05-11
CPC分类号： H04N5/2173 , G11C19/285
摘要： A digital correlated double sampling circuit employs three registers and a single clock signal to sample the output of a charge transfer device. The first register samples the reset reference value on the falling edge of the master clock cycle while the remaining two registers sample on the rising edge. The second register samples the image level and the third register samples the output of the first register, thus effecting a delay of the reset reference level. The outputs of the second and third registers, that is, the image level and the reset reference level, are differenced to provide a noise-free image signal.
摘要翻译： 数字相关双采样电路采用三个寄存器和单个时钟信号来对电荷转移装置的输出进行采样。 第一个寄存器在主时钟周期的下降沿采样复位参考值，而其余两个寄存器在上升沿采样。 第二个寄存器采样图像电平，第三个寄存器采样第一个寄存器的输出，从而影响复位参考电平的延迟。 第二和第三寄存器的输出，即图像电平和复位基准电平不同，以提供无噪声的图像信号。
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