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公开(公告)号：US07430680B2
公开(公告)日：2008-09-30
申请号：US11169006
申请日：2005-06-29
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , G06F1/12
摘要： A system and method use an aligning device to align clock signals of two logic devices before data transfer between them. In this example, the aligning device aligns a clock signal of a sequencer with a clock signal of a storage device before the sequencer transfers data to the storage device. The aligning device includes a phase detector that receives a first reference clock signal, which is used to control the storage device, and a delayed signal, which is used to control the sequencer, and generates a comparison clock signal. The comparison clock signal is filtered before being used to control a phase of a second reference clock signal, which is related to the first reference clock signal. The phase controlled second clock signal is an aligning clock signal that is feed back to a delay device to produce one or more subsequent delay device clock signals that are aligned to the storage device clock or first reference clock signal. These subsequent delay device clock signals are transmitted to the aligning device and to the sequencer before each transfer occurs.
摘要翻译： 在它们之间的数据传输之前，系统和方法使用对准装置对准两个逻辑装置的时钟信号。 在该示例中，对准装置在定序器将数据传送到存储装置之前将定序器的时钟信号与存储装置的时钟信号对准。 对准装置包括相位检测器，其接收用于控制存储装置的第一参考时钟信号和用于控制定序器的延迟信号，并产生比较时钟信号。 在用于控制与第一参考时钟信号相关的第二参考时钟信号的相位之前，对比较时钟信号进行滤波。 相位控制的第二时钟信号是对准时钟信号，其被反馈到延迟器件以产生与存储器件时钟或第一参考时钟信号对准的一个或多个后续延迟器件时钟信号。 在每次传送发生之前，这些后续的延迟装置时钟信号被发送到对准装置和定序器。
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2.发明授权Signal processing circuit for performing a pipelined matrix multiplication upon signals from several linear sensors 失效用于在几个线性传感器信号之间执行管道矩阵多路复用的信号处理电路
公开(公告)号：US5109273A
公开(公告)日：1992-04-28
申请号：US522439
申请日：1990-05-11
摘要： A signal processing circuit operates upon digitized signals from a plurality of linear color sensors that are spatially separated in the page scanning direction by a predetermined number of lines. The digitized signals are realigned in a line rephasing circuit, which provides sets of rephased color values for each scanned element of the original. A matrix multiplication is performed in a row sequential process upon the rephased signals by a group of multipliers, one multiplier for each row coefficient of the matrix. Each multiplier receives a rephased signal and a series of coefficients multiplexed into the circuit from a group of row coefficient registers. By clocking the rephased signals at a submultiple of the coefficient rate, a row-sequential matrix operation is serially performed in a pipelined manner.
摘要翻译： 信号处理电路对来自多个线性颜色传感器的数字化信号进行操作，所述多个线性颜色传感器在页面扫描方向上空间分开预定数量的行。 数字化信号在行重新定标电路中重新对准，它为原始数据的每个扫描元件提供了一组重新分配的颜色值。 通过一组乘法器对重定位信号执行矩阵乘法，对矩阵的每行行系数使用一个乘法器。 每个乘法器从一组行系数寄存器接收一个重新定位的信号和一系列被复用到电路中的系数。 通过以系数速率的倍数计时重新移动的信号，以流水线的方式串行地执行行顺序矩阵运算。
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公开(公告)号：US07515504B2
公开(公告)日：2009-04-07
申请号：US11969404
申请日：2008-01-04
IPC分类号： G11C8/00
CPC分类号： G11C7/04 , G06F13/4243 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/4076 , G11C11/4093 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , H03K2005/00052 , H03L7/0805 , H03L7/0812 , H03L7/183 , H03L7/23
摘要： A system and method are used to allow high speed communication between a circuit and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.
摘要翻译： 一种系统和方法用于允许电路和外部设备之间的高速通信。 该系统和方法包括配置为被数字控制的多个相控输出的PLL，被配置为将控制器电路的时钟与接口电路对准的偏移校准PLL以及被配置为相移输入信号的相位内插电压控制延迟线。 相位插值的模拟设计技术可精确定位高速接口所需的时钟和选通信号。 高速接口用于从外部设备发送和接收信号，例如DDR DRAM。
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公开(公告)号：US07333390B2
公开(公告)日：2008-02-19
申请号：US11287380
申请日：2005-11-28
IPC分类号： G11C8/00
CPC分类号： G11C7/04 , G06F13/4243 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/4076 , G11C11/4093 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , H03K2005/00052 , H03L7/0805 , H03L7/0812 , H03L7/183 , H03L7/23
摘要： A system and method are used to allow high speed communication between a chip and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.
摘要翻译： 使用系统和方法来允许芯片和外部设备之间的高速通信。 该系统和方法包括配置为被数字控制的多个相控输出的PLL，被配置为将控制器电路的时钟与接口电路对准的偏移校准PLL以及被配置为相移输入信号的相位内插电压控制延迟线。 相位插值的模拟设计技术可精确定位高速接口所需的时钟和选通信号。 高速接口用于从外部设备发送和接收信号，例如DDR DRAM。
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公开(公告)号：US06975557B2
公开(公告)日：2005-12-13
申请号：US10832262
申请日：2004-04-27
IPC分类号： G06F13/42 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C8/00
CPC分类号： G11C7/04 , G06F13/4243 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/4076 , G11C11/4093 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , H03K2005/00052 , H03L7/0805 , H03L7/0812 , H03L7/183 , H03L7/23
摘要： A system and method are used to allow high speed communication between a chip and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.
摘要翻译： 使用系统和方法来允许芯片和外部设备之间的高速通信。 该系统和方法包括配置为被数字控制的多个相控输出的PLL，被配置为将控制器电路的时钟与接口电路对准的偏移校准PLL以及被配置为相移输入信号的相位内插电压控制延迟线。 相位插值的模拟设计技术可精确定位高速接口所需的时钟和选通信号。 高速接口用于从外部设备发送和接收信号，例如DDR DRAM。
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公开(公告)号：US5058065A
公开(公告)日：1991-10-15
申请号：US488824
申请日：1990-02-26
申请人： Lionel J. D'Luna
发明人： Lionel J. D'Luna
IPC分类号： G06F5/06 , G06F5/10 , G11C7/12 , G11C11/401
摘要： A digital line delay architecture is provided that requires a minimum of chip space, has low power requirements, is variable or programmable in length, and is flexible to permit changes in aspect ratio. The digital line delay architecture is self-multiplexing and therefore requires no external addressing for the multiplexing function, and is particularly suited for use as a video line delay in a single chip digital image processing device. In particular, a pointer unit is employed to sequentially address a plurality of word storage locations provided in a storage unit. The pointer unit includes a number of shift-registers that sequentially shift a logic "1" along the length of the pointer unit to accomplish the addressing.
摘要翻译： 提供了一种数字线路延迟架构，其需要最小的芯片空间，具有低功率要求，可变长度或可编程长度，并且是灵活的，以允许改变纵横比。 数字线路延迟架构是自复用的，因此不需要用于复用功能的外部寻址，并且特别适合用作单芯片数字图像处理设备中的视频行延迟。 特别地，使用指针单元来顺序地寻址提供在存储单元中的多个字存储位置。 指针单元包括多个移位寄存器，其顺序地沿着指针单元的长度移位逻辑“1”以完成寻址。
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7.发明授权Real-time digital processor for producing full resolution color signals from a multi-color image sensor 失效用于从多色图像传感器生成全分辨率彩色信号的实时数字处理器
公开(公告)号：US5008739A
公开(公告)日：1991-04-16
申请号：US310419
申请日：1989-02-13
摘要： A digital processing system is described for processing luminance and chrominance signals from a single, multi-color image sensor. By concentrating signal improvements and corrections into an application-dependent post-processing phase, the pre-processing functions are isolated in a signle, generic pre-processor integrated circuit that provides fully interpolated color signals in a real-time system by utilizing a fully pipelined architecture. The pre-processor circuit separates luminance and chrominance interpolation so as to operate partly in quantized linear space and partly in quantized logarithmic space. The image signals are processed in a black reference clamp, a defect concealment circuit and a color separation and luminance interpolation circuit in linear space, using right shifts and additions to approximate predetermined multiplications. The signals are then transformed into hue signals and processed in log space for white balance and chroma (hue) interpolation. With the log green signal separately adjusted for gain, quantized red, green and blue signals are output from the pre-processor integrated circuit.
摘要翻译： 描述了用于处理来自单个多色图像传感器的亮度和色度信号的数字处理系统。 通过将信号改进和校正集中到依赖于应用的后处理阶段，预处理功能被隔离在一个通用的预处理器集成电路中，通过使用完全流水线的方式在实时系统中提供完全内插的颜色信号 建筑。 预处理器电路分离亮度和色度插值，以部分地在量化的线性空间中操作，部分地在量化对数空间中操作。 图像信号在黑色参考夹，缺陷隐藏电路和线性空间中的色分离和亮度插值电路中使用右移和相加来近似预定乘法进行处理。 然后将信号转换成色调信号，并在对数空间中进行白平衡和色度（色调）插值处理。 随着日志绿色信号单独调整增益，量化的红，绿和蓝信号从预处理器集成电路输出。
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公开(公告)号：US5374956A
公开(公告)日：1994-12-20
申请号：US889703
申请日：1992-05-29
申请人： Lionel J. D'Luna
发明人： Lionel J. D'Luna
CPC分类号： H04N9/045 , H04N2209/046
摘要： A color filter array for use with an electronic image sensor is disclosed, wherein the red and blue filter elements of the color filter array are arranged to correspond with an interleaved chrominance channel pattern. Thus, actual red and blue values are utilized to generate interleaved chrominance channel information instead of interpolated values as required by conventional CFA patterns.
摘要翻译： 公开了一种用于电子图像传感器的滤色器阵列，其中滤色器阵列的红色和蓝色滤色器元件被布置成与交错的色度通道图案对应。 因此，实际的红色和蓝色值被用于产生交错的色度信道信息，而不是传统CFA模式所要求的内插值。
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9.发明授权Single chip, mode switchable, matrix multiplier and convolver suitable for color image processing 失效单芯片，模式切换，矩阵乘法器和转换器，适用于彩色图像处理
公开(公告)号：US5195050A
公开(公告)日：1993-03-16
申请号：US570187
申请日：1990-08-20
申请人： Ken W. Hsu , Lionel J. D'Luna , Hur Jay Yeh , Glen W. Brown
发明人： Ken W. Hsu , Lionel J. D'Luna , Hur Jay Yeh , Glen W. Brown
CPC分类号： G06F17/16
摘要： An integrated circuit that uses the same coefficient registers, multipliers and adders to perform both matrix multiplication and convolution operations. The multipliers are arranged in columns and rows with the matrix multiplication adders located in the corresponding columns and with the adder for producing the convolution output located in one of the columns. A mode selection switch causes the multiplexers to change input data routing based on the mode selected. The circuit allows loading of all the coefficients or selection of hardwired coefficients. By rerouting the inputs of the multipliers using the multiplexers, the circuit can be easily configured for either mode of operation. The outputs corresponding to the columns are either output directly during matrix multiplication or provided to the convolution adder. The provision of an internal pseudo random number generator, serial inputs and outputs for test data and a signature analysis signal generating circuit allows the circuit to be easily internally tested.
摘要翻译： 使用相同系数寄存器，乘法器和加法器执行矩阵乘法和卷积运算的集成电路。 乘法器以列和行排列，矩阵乘法加法器位于相应的列中，并且加法器用于产生位于列之一中的卷积输出。 模式选择开关使得多路复用器基于所选择的模式改变输入数据路由。 电路允许加载所有系数或选择硬连线系数。 通过使用多路复用器重新路由乘法器的输入，可以容易地为任一种操作模式配置该电路。 对应于列的输出在矩阵乘法期间直接输出或提供给卷积加法器。 提供内部伪随机数发生器，用于测试数据的串行输入和输出以及签名分析信号发生电路允许电路容易地在内部测试。
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公开(公告)号：US5177704A
公开(公告)日：1993-01-05
申请号：US691793
申请日：1991-04-26
申请人： Lionel J. D'Luna
发明人： Lionel J. D'Luna
IPC分类号： G06F7/78
CPC分类号： G06F7/785
摘要： A digital storage device is provided that includes a storage unit having a plurality of word storage locations, each of the word storage locations being coupled to a corresponding read enable line and write enable line, and a pointer unit for addressing the read enable lines and the write enable lines to permit data to be written into the word storage locations in a first sequence in a first operating mode and to be retrieved from the word storage locations in a second sequence that is transposed from the first sequence in a second operating mode; and a clock generator coupled to the pointer unit which controls the operation of the pointer unit.
摘要翻译： 提供一种数字存储设备，其包括具有多个字存储位置的存储单元，每个字存储位置耦合到相应的读使能线和写使能线，以及指针单元，用于寻址读使能线和 写入使能线，以允许以第一操作模式以第一序列将数据写入字存储位置，并且以第二操作模式从第一序列转置的第二序列中的字存储位置检索; 以及耦合到指针单元的时钟发生器，其控制指针单元的操作。
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