公开(公告)号：US20060121668A1

公开(公告)日：2006-06-08

申请号：US11254338

申请日：2005-10-19

Applicant: Matthew Metz ,  Suman Datta ,  Mark Doczy ,  Jack Kavalieros ,  Justin Brask ,  Robert Chau

Inventor： Matthew Metz ,  Suman Datta ,  Mark Doczy ,  Jack Kavalieros ,  Justin Brask ,  Robert Chau

IPC: H01L21/8238

CPC classification number: H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966

Abstract: A method for making a titanium carbide layer is described. That method comprises alternately introducing a carbon containing precursor and a titanium containing precursor into a chemical vapor deposition reactor, while a substrate is maintained at a selected temperature. The reactor is operated for a sufficient time, and pulse times are selected for the carbon containing precursor and the titanium containing precursor, to form a titanium carbide layer of a desired thickness and workfunction on the substrate.

Abstract translation: 对碳化钛层的制造方法进行说明。 该方法包括在将基底保持在选定温度的同时将含碳前体和含钛前体交替引入化学气相沉积反应器。 反应器运行足够的时间，并且对于含碳的前体和含钛的前体选择脉冲时间，以在基底上形成所需厚度和功函数的碳化钛层。

公开(公告)号：US20060071285A1

公开(公告)日：2006-04-06

申请号：US10953295

申请日：2004-09-29

Applicant: Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Justin Brask ,  Robert Chau ,  Brian Doyle

Inventor： Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Justin Brask ,  Robert Chau ,  Brian Doyle

IPC: H01L29/78 ,  H01L21/8238

CPC classification number: H01L21/28079 ,  H01L21/26586 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7845

Abstract: In a metal gate replacement process, strain may be selectively induced in the channels of NMOS and PMOS transistors. For example, a material having a higher coefficient of thermal expansion than the substrate may be used to form the gate electrodes of PMOS transistors. A material with a lower coefficient of thermal expansion than that of the substrate may be used to form the gate electrodes of NMOS transistors.

Abstract translation: 在金属栅极替换工艺中，可以在NMOS和PMOS晶体管的沟道中选择性地诱发应变。 例如，可以使用具有比衬底更高的热膨胀系数的材料来形成PMOS晶体管的栅电极。 可以使用具有比基板的热膨胀系数更低的热膨胀系数的材料来形成NMOS晶体管的栅电极。

公开(公告)号：US20060060930A1

公开(公告)日：2006-03-23

申请号：US10943693

申请日：2004-09-17

Applicant: Matthew Metz ,  Clifford Boyd ,  Markus Kuhn ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Robert Chau

Inventor： Matthew Metz ,  Clifford Boyd ,  Markus Kuhn ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Robert Chau

IPC: H01L29/76 ,  H01L21/336

CPC classification number: H01L29/517 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/7833

Abstract: Gate dielectrics formed of silicates of hafnium or zirconium dioxide may be formed by atomic layer deposition. The precursors for the atomic layer deposition may include an oxidant, a silicate precursor, and a zirconium or hafnium precursor.

Abstract translation: 可以通过原子层沉积形成由铪或二氧化锆的硅酸盐形成的栅极电介质。 原子层沉积的前体可以包括氧化剂，硅酸盐前体和锆或铪前体。

公开(公告)号：US20060051924A1

公开(公告)日：2006-03-09

申请号：US10937195

申请日：2004-09-08

Applicant: Mark Doczy ,  Justin Brask ,  Jack Kavalieros ,  Uday Shah ,  Matthew Metz ,  Suman Datta ,  Ramune Nagisetty ,  Robert Chau

Inventor： Mark Doczy ,  Justin Brask ,  Jack Kavalieros ,  Uday Shah ,  Matthew Metz ,  Suman Datta ,  Ramune Nagisetty ,  Robert Chau

IPC: H01L21/336

CPC classification number: H01L21/823842

Abstract: A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, a trench within the first dielectric layer, and a second dielectric layer on the substrate. The second dielectric layer has a first part that is formed in the trench and a second part. After a first metal layer with a first workfunction is formed on the first and second parts of the second dielectric layer, part of the first metal layer is converted into a second metal layer with a second workfunction.

公开(公告)号：US20060046523A1

公开(公告)日：2006-03-02

申请号：US10925458

申请日：2004-08-25

Applicant: Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Chris Barns ,  Matthew Metz ,  Suman Datta ,  Robert Chau ,  Matt Prince ,  Anne Miller ,  Mark Buehler

Inventor： Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Chris Barns ,  Matthew Metz ,  Suman Datta ,  Robert Chau ,  Matt Prince ,  Anne Miller ,  Mark Buehler

IPC: H01L21/76

CPC classification number: H01L29/517 ,  H01L21/28079 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/66545

Abstract: Replacement metal gates may be formed by removing a polysilicon layer from a gate structure. The gate structure may be formed by patterning the polysilicon layer and depositing a spacer layer over the gate structure such that the spacer layer has a first polish rate. The spacer layer is then etched to form a sidewall spacer. An interlayer dielectric is applied over the gate structure with the sidewall spacer. The interlayer dielectric has a second polish rate higher than the first polish rate. In one embodiment, the interlayer dielectric has a lower polish rate than that of oxide.

Abstract translation: 可以通过从栅极结构去除多晶硅层来形成替代金属栅极。 栅极结构可以通过图案化多晶硅层并在栅极结构上沉积间隔层形成，使得间隔层具有第一抛光速率。 然后对间隔层进行蚀刻以形成侧壁间隔物。 在栅极结构上用侧壁间隔物施加层间电介质。 层间电介质具有比第一抛光速率高的第二抛光速率。 在一个实施例中，层间电介质具有比氧化物更低的抛光速率。

公开(公告)号：US20060046401A1

公开(公告)日：2006-03-02

申请号：US10925468

申请日：2004-08-25

Applicant: Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Matthew Metz ,  Suman Datta ,  Uday Shah ,  Robert Chau

Inventor： Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Matthew Metz ,  Suman Datta ,  Uday Shah ,  Robert Chau

IPC: H01L31/0312

CPC classification number: H01L27/092 ,  H01L21/28114 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/66545

Abstract: In a metal gate replacement process, a stack of at least two polysilicon layers or other materials may be formed. Sidewall spacers may be formed on the stack. The stack may then be planarized. Next, the upper layer of the stack may be selectively removed. Then, the exposed portions of the sidewall spacers may be selectively removed. Finally, the lower portion of the stack may be removed to form a T-shaped trench which may be filled with the metal replacement.

Abstract translation: 在金属栅极更换工艺中，可以形成至少两个多晶硅层或其它材料的堆叠。 侧壁间隔物可以形成在堆叠上。 然后可以将堆叠平坦化。 接下来，可以选择性地去除堆叠的上层。 然后，可以选择性地去除侧壁间隔物的暴露部分。 最后，堆叠的下部可以被去除以形成可以用金属替代物填充的T形沟槽。

公开(公告)号：US20060045968A1

公开(公告)日：2006-03-02

申请号：US10925573

申请日：2004-08-25

Applicant: Matthew Metz ,  Mark Brazier ,  Timothy Glassman ,  Christopher Thomas ,  Lawrence Foley ,  Christopher Parker ,  Ying Zhou ,  Markus Kuhn ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Robert Chau

Inventor： Matthew Metz ,  Mark Brazier ,  Timothy Glassman ,  Christopher Thomas ,  Lawrence Foley ,  Christopher Parker ,  Ying Zhou ,  Markus Kuhn ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Robert Chau

IPC: C23C16/00

CPC classification number: C23C16/45527

Abstract: Increasing the number of successive pulses of oxidant before applying pulses of metal precursor may improve the quality of the resulting metal or rare earth oxide films. These metal or rare earth oxide films may be utilized for high dielectric constant gate dielectrics. In addition, pulsing the oxidant during the pre-stabilization period may be advantageous. Also, using more pulses of oxidant than the pulses of precursor may reduce chlorine concentration in the resulting films.

Abstract translation: 在施加金属前体的脉冲之前增加氧化剂的连续脉冲数可以提高所得金属或稀土氧化物膜的质量。 这些金属或稀土氧化物膜可用于高介电常数栅极电介质。 此外，在预稳定化期间脉冲氧化剂可能是有利的。 此外，使用比前体脉冲更多的氧化剂脉冲可以降低所得膜中的氯浓度。

公开(公告)号：US20060024892A1

公开(公告)日：2006-02-02

申请号：US10900666

申请日：2004-07-28

Applicant: Justin Brask ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Suman Datta ,  Uday Shah ,  Robert Chau

Inventor： Justin Brask ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Suman Datta ,  Uday Shah ,  Robert Chau

IPC: H01L21/336

CPC classification number: H01L29/517 ,  H01L21/265 ,  H01L21/28079 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/823842 ,  H01L29/495

Abstract: A metal gate transistor may include a metal layer over a high dielectric constant dielectric layer. The dielectric layer abstracts electronegativity from said metal layer, altering its workfunction. The workfunction of the metal layer may be set to compensate for the dielectric layer abstraction.

Abstract translation: 金属栅极晶体管可以包括在高介电常数介电层上的金属层。 电介质层从所述金属层提取电负性，改变其功能。 可以设置金属层的功函数以补偿介电层抽象。

公开(公告)号：US20060008968A1

公开(公告)日：2006-01-12

申请号：US10885958

申请日：2004-07-06

Applicant: Justin Brask ,  Chris Barns ,  Mark Doczy ,  Uday Shah ,  Jack Kavalieros ,  Matthew Metz ,  Suman Datta ,  Anne Miller ,  Robert Chau

Inventor： Justin Brask ,  Chris Barns ,  Mark Doczy ,  Uday Shah ,  Jack Kavalieros ,  Matthew Metz ,  Suman Datta ,  Anne Miller ,  Robert Chau

IPC: H01L21/8238

CPC classification number: H01L29/66545 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28229 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, forming a trench within the dielectric layer, and forming a high-k gate dielectric layer within the trench. After forming a first metal layer on the high-k gate dielectric layer, a second metal layer is formed on the first metal layer. At least part of the second metal layer is removed from above the dielectric layer using a polishing step, and additional material is removed from above the dielectric layer using an etch step.

Abstract translation: 描述制造半导体器件的方法。 该方法包括在衬底上形成电介质层，在电介质层内形成沟槽，并在沟槽内形成高k栅介质层。 在高k栅介质层上形成第一金属层之后，在第一金属层上形成第二金属层。 使用抛光步骤从电介质层上方去除第二金属层的至少一部分，并且使用蚀刻步骤从电介质层上方除去附加材料。

公开(公告)号：US20060008954A1

公开(公告)日：2006-01-12

申请号：US11218355

申请日：2005-09-02

Applicant: Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Scott Hareland ,  Matthew Metz ,  Chris Barns ,  Robert Chau

Inventor： Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Scott Hareland ,  Matthew Metz ,  Chris Barns ,  Robert Chau

IPC: H01L31/119 ,  H01L31/113 ,  H01L31/062 ,  H01L29/94 ,  H01L29/76 ,  H01L21/84 ,  H01L21/00

CPC classification number: H01L29/517 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/66545 ,  Y10S438/926

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods comprise providing a substrate comprising a first transistor structure comprising an n-type gate material and second transistor structure comprising a p-type gate material, selectively removing the n-type gate material to form a recess in the first gate structure, and then filling the recess with an n-type metal gate material.

Abstract translation: 描述形成微电子器件的方法和相关结构。 这些方法包括提供包括包括n型栅极材料的第一晶体管结构和包括p型栅极材料的第二晶体管结构的衬底，选择性地去除n型栅极材料以在第一栅极结构中形成凹陷，然后 用n型金属栅极材料填充凹部。