公开(公告)号：US08364433B1

公开(公告)日：2013-01-29

申请号：US12338792

申请日：2008-12-18

申请人： Mansour Keramat ,  Syed S. Islam ,  Mehrdad Heshami

发明人： Mansour Keramat ,  Syed S. Islam ,  Mehrdad Heshami

IPC分类号： G01R27/00 ,  G01R35/00

CPC分类号： H03H11/1291 ,  H03H2210/043

摘要： A calibration system employed for use with a resistance capacitance (RC) filter having resistors and capacitors with parasitic capacitance associated therewith. The calibration system has a digital calibration circuit receiving a time constant signal and generating, based thereon, a control word of N digital bits. The calibration system includes an analog monitor circuit having monitor capacitance assembly having a particular equivalent resistor and capacitor configuration. The analog monitor circuit generates the time constant signal and includes N switches, where each switch is controlled by one of the N bits of the control word, each switch is configured to connect or disconnect one or more capacitors of the monitor capacitor assembly thereby generating a time constant signal that represents the time constant of the RC integrated filter.

摘要翻译： 一种校准系统，用于与具有与其相关的寄生电容的电阻和电容器的电阻电容（RC）滤波器。 校准系统具有接收时间常数信号的数字校准电路，并且基于此产生N个数字位的控制字。 校准系统包括具有具有特定等效电阻器和电容器配置的监视电容组件的模拟监视器电路。 模拟监视器电路产生时间常数信号并且包括N个开关，其中每个开关由控制字的N位之一控制，每个开关被配置为连接或断开监视电容器组件的一个或多个电容器，从而产生 时间常数信号，表示RC集成滤波器的时间常数。

公开(公告)号：US20120149322A1

公开(公告)日：2012-06-14

申请号：US13399971

申请日：2012-02-17

申请人： Timothy C. Kuo ,  Mansour Keramat ,  Edward Wai Yeung Liu

发明人： Timothy C. Kuo ,  Mansour Keramat ,  Edward Wai Yeung Liu

IPC分类号： H04B1/06

CPC分类号： H04W52/367 ,  H04B17/0085 ,  H04B17/21 ,  H04W52/16 ,  H04W52/40

摘要： An apparatus for calibrating gain of an radio frequency receiver (“Rx”) is disclosed to provide, among other things, a structure for performing in-situ gain calibration of an RF integrated circuit over time and/or over temperature without removing the RF integrated circuit from its operational configuration, especially when the gain of the RF integrated circuit is susceptible to variations in process, such as inherent with the CMOS process. In one embodiment, an exemplary apparatus includes a thermal noise generator configured to generate thermal noise as a calibrating signal into an input of an Rx path of an RF integrated circuit. The apparatus also includes a calibrator configured to first measure an output signal from an output of the Rx path, and then adjust a gain of the Rx path based on the thermal noise. In one embodiment, the thermal noise generator further includes a termination resistance and/or impedance.

摘要翻译： 公开了一种用于校准射频接收机（“Rx”）的增益的装置，其特征在于提供一种用于在不消除RF集成的情况下随时间和/或过温度进行RF集成电路的原位增益校准的结构 特别是当RF集成电路的增益易受诸如CMOS工艺固有的工艺变化影响时。 在一个实施例中，示例性装置包括热噪声发生器，其被配置为产生作为校准信号的热噪声到RF集成电路的Rx路径的输入中。 该装置还包括校准器，其被配置为首先测量来自Rx路径的输出的输出信号，然后基于热噪声来调整Rx路径的增益。 在一个实施例中，热噪声发生器还包括端接电阻和/或阻抗。

公开(公告)号：US07977762B1

公开(公告)日：2011-07-12

申请号：US12331386

申请日：2008-12-09

申请人： Mansour Keramat ,  Mehrdad Heshami ,  Syed S. Islam

发明人： Mansour Keramat ,  Mehrdad Heshami ,  Syed S. Islam

IPC分类号： H01L29/06

CPC分类号： H01L23/585 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit (IC) is disclosed to include a central area of the IC that is partitioned into a first section containing at least one digital circuit and a second section containing at least one analog circuit; and a guard strip (or shield) that is within the central area and that is positioned within between the digital circuit and the analog circuit. The shield or guard strip comprises of n-well and p-tap regions that separate digital and analog circuits.

摘要翻译： 公开了一种集成电路（IC），其包括被分割成包含至少一个数字电路的第一部分和包含至少一个模拟电路的第二部分的IC的中心区域; 以及位于中央区域内且位于数字电路和模拟电路之间的保护条（或屏蔽）。 屏蔽或保护条包括分开数字和模拟电路的n阱和p抽头区域。

公开(公告)号：US07542749B1

公开(公告)日：2009-06-02

申请号：US11955101

申请日：2007-12-12

申请人： Tao Liu ,  Mansour Keramat ,  Edward Wai Yeung Liu ,  Mehrdad Heshami ,  Timothy C. Kuo

发明人： Tao Liu ,  Mansour Keramat ,  Edward Wai Yeung Liu ,  Mehrdad Heshami ,  Timothy C. Kuo

IPC分类号： H04B1/06

CPC分类号： H04B15/02 ,  H04B2215/067

摘要： A system, method and system are disclosed for using a variable frequency clock generator to synchronize an average data rate over intervals of time in a variable clock domain to make it equal to a fixed data rate in a fixed clock domain while reducing electromagnetic interference, among other things. In various embodiments, setting the data rates equal to each other minimizes storage used to transition data signals between clock domains. In one embodiment, a variable frequency clock generator includes a phase modulator configured to form a variable frequency clock. Also, the variable clock generator is configured to maintain an average frequency over specific periods of time for the range of discrete frequencies. The phase-offset controller sets an average clock having substantially no offset between a fixed data rate in the fixed clock domain and an average data rate in the variable clock domain.

公开(公告)号：US07499690B1

公开(公告)日：2009-03-03

申请号：US11954857

申请日：2007-12-12

申请人： Tao Liu ,  Mansour Keramat ,  Edward Wai Yeung Liu ,  Mehrdad Heshami ,  Timothy C. Kuo

发明人： Tao Liu ,  Mansour Keramat ,  Edward Wai Yeung Liu ,  Mehrdad Heshami ,  Timothy C. Kuo

IPC分类号： H04B1/06

CPC分类号： H04B15/02 ,  H04B2215/067

摘要： A system, method and system are disclosed for using a variable frequency clock generator to synchronize an average data rate over intervals of time in a variable clock domain to make it equal to a fixed data rate in a fixed clock domain while reducing electromagnetic interference, among other things. In various embodiments, setting the data rates equal to each other minimizes storage used to transition data signals between clock domains. In one embodiment, a variable frequency clock generator includes a phase modulator configured to form a variable frequency clock. Also, the variable clock generator is configured to maintain an average frequency over specific periods of time for the range of discrete frequencies. The phase-offset controller sets an average clock having substantially no offset between a fixed data rate in the fixed clock domain and an average data rate in the variable clock domain.

摘要翻译： 公开了一种系统，方法和系统，用于使用可变频率时钟发生器在可变时钟域中的时间间隔上同步平均数据速率，使其等于固定时钟域中的固定数据速率，同时减少电磁干扰，其中 其他事情。 在各种实施例中，将数据速率设置为彼此相等最小化用于在时钟域之间转换数据信号的存储。 在一个实施例中，可变频率时钟发生器包括被配置为形成可变频率时钟的相位调制器。 此外，可变时钟发生器被配置为在离散频率的范围内保持特定时间段的平均频率。 相位偏移控制器设置在固定时钟域中的固定数据速率与可变时钟域中的平均数据速率之间基本上没有偏移的平均时钟。

公开(公告)号：US07403150B1

公开(公告)日：2008-07-22

申请号：US11524989

申请日：2006-09-20

申请人： Mehrdad Heshami ,  Mansour Keramat

发明人： Mehrdad Heshami ,  Mansour Keramat

IPC分类号： H03M1/36

CPC分类号： H03M1/0607 ,  H03M1/361

摘要： An analog-to-digital converter architecture is described. An analog-to-digital converter circuit includes a switched capacitor circuit structure to receive an input voltage signal and one or more reference voltage signals. The analog-to-digital converter circuit also includes a comparator device array coupled to the switched capacitor circuit structure. The comparator device array further includes multiple comparator devices coupled in parallel, each comparator device having a pair of inputs coupled to the switched capacitor circuit structure to receive a voltage output signal from the switched capacitor circuit, a voltage value of the voltage output signal being calculated as a difference between an input voltage value of the input voltage signal and a predetermined value of the reference voltage signal, which is dependent on the position of the respective comparator device within the comparator device array, each comparator device experiencing an identical common mode voltage input within the analog-to-digital converter circuit.

摘要翻译： 描述了一种模拟 - 数字转换器架构。 模拟 - 数字转换器电路包括用于接收输入电压信号和一个或多个参考电压信号的开关电容器电路结构。 模数转换器电路还包括耦合到开关电容器电路结构的比较器器件阵列。 比较器器件阵列还包括并联耦合的多个比较器器件，每个比较器器件具有耦合到开关电容器电路结构的一对输入端，以接收来自开关电容器电路的电压输出信号，计算出电压输出信号的电压值 作为输入电压信号的输入电压值与参考电压信号的预定值之间的差异，其取决于比较器装置阵列内的各个比较器装置的位置，每个比较器装置经历相同的共模电压输入 在模数转换器电路内。

公开(公告)号：US08614472B1

公开(公告)日：2013-12-24

申请号：US13214136

申请日：2011-08-19

申请人： Syed S. Islam ,  Mansour Keramat

发明人： Syed S. Islam ,  Mansour Keramat

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L23/5223 ,  H01L28/86 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit metal oxide metal (MOM) variable capacitor includes a first plate; one or more pairs of second plates positioned on both sides of the first plate; one or more pairs of control plates positioned on both sides of the first plate and positioned between the pairs of second plates; and a switch coupled to each control plate and a fixed potential.

摘要翻译： 集成电路金属氧化物金属（MOM）可变电容器包括第一板; 一对或多对定位在第一板两侧的第二板; 一对或多对控制板，其位于所述第一板的两侧并位于所述第二板对之间; 以及耦合到每个控制板和固定电位的开关。

公开(公告)号：US20130120885A1

公开(公告)日：2013-05-16

申请号：US13297236

申请日：2011-11-15

申请人： Mansour Keramat ,  Tim Kuo

发明人： Mansour Keramat ,  Tim Kuo

IPC分类号： H02H9/04

CPC分类号： H01L27/0292

摘要： Systems and methods are disclosed to reduce pin count in an integrated circuit with digital and analog circuits on-chip by receiving power (VDD) input at a digital power input pad that provides electrostatic discharge (ESD) protection but substantially no current for on-chip analog circuits; filtering noise from the digital power input pad with a filter; and coupling a low noise analog power input pad internal to the integrated circuit to the filter and an analog circuit or a low noise singled ended radio frequency circuit without requiring an external analog power pin.

摘要翻译： 公开了系统和方法，以通过在数字电源输入焊盘处接收功率（VDD）输入的芯片上的数字和模拟电路来减少集成电路中的引脚数，该数字电源输入焊盘提供静电放电（ESD）保护，但基本上没有片上电流 模拟电路; 用滤波器滤除数字电源输入板的噪声; 并将集成电路内部的低噪声模拟电源输入焊盘耦合到滤波器以及模拟电路或低噪声单端射频电路，而无需外部模拟电源引脚。

公开(公告)号：US20130120177A1

公开(公告)日：2013-05-16

申请号：US13297240

申请日：2011-11-15

申请人： Mansour Keramat ,  Yuan-Ju Chao

发明人： Mansour Keramat ,  Yuan-Ju Chao

IPC分类号： G05F3/02 ,  H03M1/66

CPC分类号： G05F3/262 ,  H03M1/745

摘要： Systems and methods are disclosed for performing data conversion by matching current sources using a thin oxide device; and minimizing voltage stress on the thin oxide device during operation or power down.

摘要翻译： 公开了用于通过使用薄氧化物装置匹配电流源来进行数据转换的系统和方法; 并在运行或掉电期间最小化薄氧化物装置上的电压应力。

公开(公告)号：US07606546B1

公开(公告)日：2009-10-20

申请号：US12106167

申请日：2008-04-18

申请人： Tao Liu ,  Mansour Keramat ,  Edward Wai Yeung Liu ,  Mehrdad Heshami ,  Timothy C. Kuo

发明人： Tao Liu ,  Mansour Keramat ,  Edward Wai Yeung Liu ,  Mehrdad Heshami ,  Timothy C. Kuo

IPC分类号： H04B1/06

CPC分类号： H04B15/02 ,  H04B2215/067

摘要： A system, method and system are disclosed for using a variable frequency clock generator to synchronize an average data rate over intervals of time in a variable clock domain to make it equal to a fixed data rate in a fixed clock domain while reducing electromagnetic interference, among other things. In various embodiments, setting the data rates equal to each other minimizes storage used to transition data signals between clock domains. In one embodiment, a variable frequency clock generator includes a phase modulator configured to form a variable frequency clock. Also, the variable clock generator is configured to maintain an average frequency over specific periods of time for the range of discrete frequencies. The phase-offset controller sets an average clock having substantially no offset between a fixed data rate in the fixed clock domain and an average data rate in the variable clock domain.