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28 条记录 (耗时 0.02 秒)

    Accurate resistance capacitance (RC) time constant calibration with metal-oxide-metal (MOM) capacitors for precision frequency response of integrated filters
    1.
    发明授权
    Accurate resistance capacitance (RC) time constant calibration with metal-oxide-metal (MOM) capacitors for precision frequency response of integrated filters 失效
    使用金属氧化物金属（MOM）电容器对集成滤波器进行精确频率响应的精确电阻电容（RC）时间常数校准

    公开(公告)号：US08364433B1

    公开(公告)日：2013-01-29

    申请号：US12338792

    申请日：2008-12-18

    申请人： Mansour Keramat ,  Syed S. Islam ,  Mehrdad Heshami

    发明人： Mansour Keramat ,  Syed S. Islam ,  Mehrdad Heshami

    IPC分类号： G01R27/00 ,  G01R35/00

    CPC分类号： H03H11/1291 ,  H03H2210/043

    摘要： A calibration system employed for use with a resistance capacitance (RC) filter having resistors and capacitors with parasitic capacitance associated therewith. The calibration system has a digital calibration circuit receiving a time constant signal and generating, based thereon, a control word of N digital bits. The calibration system includes an analog monitor circuit having monitor capacitance assembly having a particular equivalent resistor and capacitor configuration. The analog monitor circuit generates the time constant signal and includes N switches, where each switch is controlled by one of the N bits of the control word, each switch is configured to connect or disconnect one or more capacitors of the monitor capacitor assembly thereby generating a time constant signal that represents the time constant of the RC integrated filter.

    摘要翻译： 一种校准系统，用于与具有与其相关的寄生电容的电阻和电容器的电阻电容（RC）滤波器。 校准系统具有接收时间常数信号的数字校准电路，并且基于此产生N个数字位的控制字。 校准系统包括具有具有特定等效电阻器和电容器配置的监视电容组件的模拟监视器电路。 模拟监视器电路产生时间常数信号并且包括N个开关，其中每个开关由控制字的N位之一控制，每个开关被配置为连接或断开监视电容器组件的一个或多个电容器，从而产生 时间常数信号，表示RC集成滤波器的时间常数。

    Seal ring for reducing noise coupling within a system-on-a-chip (SoC)
    3.
    发明授权
    Seal ring for reducing noise coupling within a system-on-a-chip (SoC) 有权
    用于减少片上系统（SoC）内的噪声耦合的密封环

    公开(公告)号：US07898056B1

    公开(公告)日：2011-03-01

    申请号：US12331373

    申请日：2008-12-09

    申请人： Mansour Keramat ,  Syed S. Islam ,  Mehrdad Heshami

    发明人： Mansour Keramat ,  Syed S. Islam ,  Mehrdad Heshami

    IPC分类号： H01L29/06 ,  H01L23/552

    CPC分类号： H01L23/585 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed is a seal-ring architecture that can minimize noise injection from noisy digital circuits to sensitive analog and/or radio frequency (RF) circuits in system-on-a-chip (SoC) applications. In order to improve the isolation, the seal-ring structure contains cuts and ground connections to the segment which is close to the analog circuits. The cuts are such that the architecture is fully compatible with standard design rules and that the mechanical strength of the seal rings is not significantly sacrificed. Some embodiments also include a grounded p-tap ring between the analog circuits and the inner seal ring in order to improve isolation. Some embodiments also include a guard strip between the analog circuits and the digital circuits to minimize the noise injection through the substrate.

    摘要翻译： 公开了一种密封环结构，其可以将系统级芯片（SoC）应用中的噪声数字电路的噪声注入最小化到敏感的模拟和/或射频（RF）电路。 为了改善隔离度，密封圈结构包含与靠近模拟电路的段的切割和接地连接。 切割使得该结构与标准设计规则完全兼容，并且密封环的机械强度不被显着牺牲。 一些实施例还包括在模拟电路和内密封环之间的接地p抽头环，以改善隔离。 一些实施例还包括模拟电路和数字电路之间的保护条，以最小化通过衬底的噪声注入。

    Fabricated U-shaped capacitor for a digital-to-analog converter
    5.
    发明授权
    Fabricated U-shaped capacitor for a digital-to-analog converter 失效
    用于数模转换器的制造U形电容器

    公开(公告)号：US07456462B1

    公开(公告)日：2008-11-25

    申请号：US11371145

    申请日：2006-03-07

    申请人： Mehrdad Heshami ,  Mansour Keramat

    发明人： Mehrdad Heshami ,  Mansour Keramat

    IPC分类号： H01L29/94

    CPC分类号： H01L28/91 ,  H01L23/5223 ,  H01L28/87 ,  H01L2924/0002 ,  H03M1/468 ,  H03M1/804 ,  H01L2924/00

    摘要： A layered capacitor having top and bottom plates formed from multiple layers. The capacitor has a bottom layer comprising a bottom plate portion and at least one upper layer, each upper layer comprising top and bottom plate portions. A first set of vias connect the bottom plate portions and a second set of vias connect the top plate portions. The bottom plate portions and the first set of vias comprise a U-shaped bottom plate and the top plate portions and the second set of vias comprise a top plate of the capacitor device. The layers may comprise metal layers produced using semiconductor fabrication methods. Also provided is a capacitor array having two or more capacitors where connectors connect all top plate portions of the capacitors. The capacitor array may be used in a capacitive DAC, which may be used in a SAR ADC.

    摘要翻译： 具有由多层形成的顶板和底板的分层电容器。 电容器具有包括底板部分和至少一个上层的底层，每个上层包括顶板部分和底板部分。 第一组通孔连接底板部分，第二组通孔连接顶板部分。 底板部分和第一组通孔包括U形底板，并且顶板部分和第二组通孔包括电容器装置的顶板。 这些层可以包括使用半导体制造方法制造的金属层。 还提供了具有两个或更多个电容器的电容器阵列，其中连接器连接电容器的所有顶板部分。 电容器阵列可用于可用于SAR ADC的电容DAC。

    Fabricated cylinder capacitor for a digital-to-analog converter
    6.
    发明授权
    Fabricated cylinder capacitor for a digital-to-analog converter 失效
    用于数模转换器的制造圆柱电容器

    公开(公告)号：US07473955B1

    公开(公告)日：2009-01-06

    申请号：US11371148

    申请日：2006-03-07

    申请人： Mehrdad Heshami ,  Mansour Keramat

    发明人： Mehrdad Heshami ,  Mansour Keramat

    IPC分类号： H01L29/94

    CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A fabricated cylinder capacitor having two or more layers is provided, each layer having a bottom plate and top plate portions. A first set of vias connect the bottom plate portions and a second set of vias connect the top plate portions. The bottom plate portions and the first set of vias comprise a bottom plate and the top plate portions and the second set of vias comprise a top plate of the capacitor. The layers may comprise five metal layers and may be produced using semiconductor fabrication methods. Also provided is a capacitor array having two or more cylinder capacitors where a set of connectors connect all top plates of the capacitors. The capacitor array may be used in a capacitive DAC, the capacitors being connected according to the architecture of the DAC. The capacitive DAC may be used in a SAR ADC.

    摘要翻译： 提供具有两层或更多层的制造的圆筒电容器，每层具有底板和顶板部分。 第一组通孔连接底板部分，第二组通孔连接顶板部分。 底板部分和第一组通孔包括底板，并且顶板部分和第二组通孔包括电容器的顶板。 这些层可以包括五个金属层，并且可以使用半导体制造方法制造。 还提供了具有两个或更多个气缸电容器的电容器阵列，其中一组连接器连接电容器的所有顶板。 电容器阵列可用于电容式DAC，电容器根据DAC的结构进行连接。 电容式DAC可用于SAR ADC。

    Variable frequency clock generator for synchronizing data rates between clock domains in radio frequency wireless communication systems
    8.
    发明授权
    Variable frequency clock generator for synchronizing data rates between clock domains in radio frequency wireless communication systems 有权
    可变频时钟发生器，用于在射频无线通信系统中的时钟域之间同步数据速率

    公开(公告)号：US07499690B1

    公开(公告)日：2009-03-03

    申请号：US11954857

    申请日：2007-12-12

    申请人： Tao Liu ,  Mansour Keramat ,  Edward Wai Yeung Liu ,  Mehrdad Heshami ,  Timothy C. Kuo

    发明人： Tao Liu ,  Mansour Keramat ,  Edward Wai Yeung Liu ,  Mehrdad Heshami ,  Timothy C. Kuo

    IPC分类号： H04B1/06

    CPC分类号： H04B15/02 ,  H04B2215/067

    摘要： A system, method and system are disclosed for using a variable frequency clock generator to synchronize an average data rate over intervals of time in a variable clock domain to make it equal to a fixed data rate in a fixed clock domain while reducing electromagnetic interference, among other things. In various embodiments, setting the data rates equal to each other minimizes storage used to transition data signals between clock domains. In one embodiment, a variable frequency clock generator includes a phase modulator configured to form a variable frequency clock. Also, the variable clock generator is configured to maintain an average frequency over specific periods of time for the range of discrete frequencies. The phase-offset controller sets an average clock having substantially no offset between a fixed data rate in the fixed clock domain and an average data rate in the variable clock domain.

    摘要翻译： 公开了一种系统，方法和系统，用于使用可变频率时钟发生器在可变时钟域中的时间间隔上同步平均数据速率，使其等于固定时钟域中的固定数据速率，同时减少电磁干扰，其中 其他事情。 在各种实施例中，将数据速率设置为彼此相等最小化用于在时钟域之间转换数据信号的存储。 在一个实施例中，可变频率时钟发生器包括被配置为形成可变频率时钟的相位调制器。 此外，可变时钟发生器被配置为在离散频率的范围内保持特定时间段的平均频率。 相位偏移控制器设置在固定时钟域中的固定数据速率与可变时钟域中的平均数据速率之间基本上没有偏移的平均时钟。

    Analog-to-digital converter architecture using a capacitor array structure
    9.
    发明授权
    Analog-to-digital converter architecture using a capacitor array structure 有权
    模数转换器架构采用电容阵列结构

    公开(公告)号：US07403150B1

    公开(公告)日：2008-07-22

    申请号：US11524989

    申请日：2006-09-20

    申请人： Mehrdad Heshami ,  Mansour Keramat

    发明人： Mehrdad Heshami ,  Mansour Keramat

    IPC分类号： H03M1/36

    CPC分类号： H03M1/0607 ,  H03M1/361

    摘要： An analog-to-digital converter architecture is described. An analog-to-digital converter circuit includes a switched capacitor circuit structure to receive an input voltage signal and one or more reference voltage signals. The analog-to-digital converter circuit also includes a comparator device array coupled to the switched capacitor circuit structure. The comparator device array further includes multiple comparator devices coupled in parallel, each comparator device having a pair of inputs coupled to the switched capacitor circuit structure to receive a voltage output signal from the switched capacitor circuit, a voltage value of the voltage output signal being calculated as a difference between an input voltage value of the input voltage signal and a predetermined value of the reference voltage signal, which is dependent on the position of the respective comparator device within the comparator device array, each comparator device experiencing an identical common mode voltage input within the analog-to-digital converter circuit.

    摘要翻译： 描述了一种模拟 - 数字转换器架构。 模拟 - 数字转换器电路包括用于接收输入电压信号和一个或多个参考电压信号的开关电容器电路结构。 模数转换器电路还包括耦合到开关电容器电路结构的比较器器件阵列。 比较器器件阵列还包括并联耦合的多个比较器器件，每个比较器器件具有耦合到开关电容器电路结构的一对输入端，以接收来自开关电容器电路的电压输出信号，计算出电压输出信号的电压值 作为输入电压信号的输入电压值与参考电压信号的预定值之间的差异，其取决于比较器装置阵列内的各个比较器装置的位置，每个比较器装置经历相同的共模电压输入 在模数转换器电路内。

    Radio frequency antenna system and high-speed digital data link to reduce electromagnetic interference for wireless communications
    10.
    发明授权
    Radio frequency antenna system and high-speed digital data link to reduce electromagnetic interference for wireless communications 有权
    射频天线系统和高速数字数据链路，以减少无线通信的电磁干扰

    公开(公告)号：US07558348B1

    公开(公告)日：2009-07-07

    申请号：US11132757

    申请日：2005-05-18

    申请人： Tao Liu ,  Mansour Keramat ,  Mehrdad Heshami ,  Feng Bao ,  Timothy C. Kuo ,  Douglas J. Hogberg ,  Bo Liang ,  Edward Wai Yeung Liu

    发明人： Tao Liu ,  Mansour Keramat ,  Mehrdad Heshami ,  Feng Bao ,  Timothy C. Kuo ,  Douglas J. Hogberg ,  Bo Liang ,  Edward Wai Yeung Liu

    IPC分类号： H03D1/04

    CPC分类号： H04B1/40 ,  H04B15/02 ,  H04B2215/067

    摘要： A radio frequency antenna system and high-speed digital data link are disclosed to, among other things, reduce electromagnetic interference (“EMI”) at relatively high data rates while reducing the manufacturing complexities associated with conventional data links. In one embodiment, a radio frequency (“RF”) antenna system includes an antenna and an RF radio coupled to the antenna for receiving wireless RF signals. In particular, the RF radio is configured to digitize RF signals at a fixed data rate to form digitized data signals and to apply the digitized data signals at a variable data rate to a high-speed digital link. The variable data rate distributes the signal energy of the digitized data signals over one or more bands of frequencies, thereby beneficially altering an EMI spectral profile describing emissions that develop as the digitized data signals are transported through a channel.

    摘要翻译： 公开了一种射频天线系统和高速数字数据链路，其中除了别的以外，在相对高的数据速率下降低电磁干扰（“EMI”），同时降低了与常规数据链路相关联的制造复杂性。 在一个实施例中，射频（“RF”）天线系统包括耦合到天线的天线和RF无线电，用于接收无线RF信号。 特别地，RF无线电被配置为以固定数据速率数字化RF信号以形成数字化数据信号，并以可变数据速率将数字化数据信号应用于高速数字链路。 可变数据速率通过一个或多个频率频带分配数字化数据信号的信号能量，从而有益地改变描述随着数字化数据信号通过信道传送而发展的辐射的EMI频谱分布。