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    LOW NOISE ESD PROTECTION FOR SOCs WITH ANALOG OR RADIO FREQUENCY DEVICES
    1.
    发明申请
    LOW NOISE ESD PROTECTION FOR SOCs WITH ANALOG OR RADIO FREQUENCY DEVICES 审中-公开
    具有模拟或无线电频率设备的SOC的低噪声ESD保护

    公开(公告)号：US20130120885A1

    公开(公告)日：2013-05-16

    申请号：US13297236

    申请日：2011-11-15

    申请人： Mansour Keramat ,  Tim Kuo

    发明人： Mansour Keramat ,  Tim Kuo

    IPC分类号： H02H9/04

    CPC分类号： H01L27/0292

    摘要： Systems and methods are disclosed to reduce pin count in an integrated circuit with digital and analog circuits on-chip by receiving power (VDD) input at a digital power input pad that provides electrostatic discharge (ESD) protection but substantially no current for on-chip analog circuits; filtering noise from the digital power input pad with a filter; and coupling a low noise analog power input pad internal to the integrated circuit to the filter and an analog circuit or a low noise singled ended radio frequency circuit without requiring an external analog power pin.

    摘要翻译： 公开了系统和方法，以通过在数字电源输入焊盘处接收功率（VDD）输入的芯片上的数字和模拟电路来减少集成电路中的引脚数，该数字电源输入焊盘提供静电放电（ESD）保护，但基本上没有片上电流 模拟电路; 用滤波器滤除数字电源输入板的噪声; 并将集成电路内部的低噪声模拟电源输入焊盘耦合到滤波器以及模拟电路或低噪声单端射频电路，而无需外部模拟电源引脚。

    Bypass capacitor with reduced leakage current and power-down control
    2.
    发明授权
    Bypass capacitor with reduced leakage current and power-down control 失效
    旁路电容器具有降低的漏电流和掉电控制

    公开(公告)号：US08400746B1

    公开(公告)日：2013-03-19

    申请号：US12956808

    申请日：2010-11-30

    申请人： Mansour Keramat ,  Sudharsan Kanagaraj

    发明人： Mansour Keramat ,  Sudharsan Kanagaraj

    IPC分类号： H02H3/22

    CPC分类号： H01L27/0629 ,  G06F1/32 ,  H01L27/0207 ,  H01L29/94

    摘要： An integrated circuit is disclosed to bypass transients between first and second nodes. The circuit includes a first bypass capacitor implemented as a metal oxide semiconductor (MOS) transistor and coupled to a first node; and a switch coupled to the first bypass capacitor and the second node, the switch preventing leakage current from passing through the first bypass capacitor during power down.

    摘要翻译： 公开了一种用于绕过第一和第二节点之间的瞬变的集成电路。 电路包括实现为金属氧化物半导体（MOS）晶体管并耦合到第一节点的第一旁路电容器; 以及耦合到所述第一旁路电容器和所述第二节点的开关，所述开关在断电期间防止漏电流通过所述第一旁路电容器。

    Clocking scheme for efficient digital noise reduction in mixed-signal systems-on-chip
    3.
    发明授权
    Clocking scheme for efficient digital noise reduction in mixed-signal systems-on-chip 有权
    用于片上混合信号系统中高效数字降噪的时钟方案

    公开(公告)号：US07920006B1

    公开(公告)日：2011-04-05

    申请号：US12338772

    申请日：2008-12-18

    申请人： Mansour Keramat ,  Keivan Etessam Yazdani

    发明人： Mansour Keramat ,  Keivan Etessam Yazdani

    IPC分类号： G06F1/04

    CPC分类号： G06F1/06

    摘要： In one embodiment of the present invention, a clock generator circuit receives a clock signal having a period. The clock signal is employed by a digital circuit that is resident on the same substrate as an analog circuit, the digital circuit generates disturbance climaxes at clock edges that propagate through the substrate to the analog circuit. A clock generator circuit generates a plurality of clock signals, with each clock signal having a unique rate, wherein during a temporal gap, defined by the time between a last disturbance climax and a next sampling time of the clock signal, clock edges of any of the plurality of clock signals are avoided.

    摘要翻译： 在本发明的一个实施例中，时钟发生器电路接收具有周期的时钟信号。 时钟信号由驻留在与模拟电路相同的衬底上的数字电路采用，数字电路在时钟沿产生通过衬底传播到模拟电路的干扰高潮。 时钟发生器电路产生多个时钟信号，其中每个时钟信号具有唯一的速率，其中在由时钟信号的最后一个干扰高峰和下一个采样时间之间的时间限定的时间间隙期间， 避免了多个时钟信号。

    Analog-to-digital converter (ADC) with reduced jitter sensitivity and power consumption
    4.
    发明授权
    Analog-to-digital converter (ADC) with reduced jitter sensitivity and power consumption 有权
    模数转换器（ADC）具有降低的抖动灵敏度和功耗

    公开(公告)号：US07852248B1

    公开(公告)日：2010-12-14

    申请号：US12331369

    申请日：2008-12-09

    申请人： Mansour Keramat ,  Ali Agah ,  Ali Tabatabaei

    发明人： Mansour Keramat ,  Ali Agah ,  Ali Tabatabaei

    IPC分类号： H03M3/00

    CPC分类号： H03M3/372 ,  H03M3/458

    摘要： In one embodiment of the present invention, at least at one stage of a Sigma-Delta analog-to-digital converter (ADC) is disclosed to include means for receiving a voltage at least one of the inputs of an operational amplifier, the operational amplifier having at least one output coupled to the at least one of the inputs via an at least one integration capacitor, means for transforming the voltage to a current and means for integrating the current on the at least one of the integration capacitors, during integration time and varying the resistance of at least one of a variable resistors coupled to the operational amplifier during integration time.

    摘要翻译： 在本发明的一个实施例中，公开了Sigma-Delta模数转换器（ADC）的至少一个阶段，以包括用于接收运算放大器的至少一个输入的电压的装置，运算放大器 具有经由至少一个积分电容器耦合到所述至少一个输入的至少一个输出，用于将所述电压转换为电流的装置，以及用于在所述积分时间期间将所述电流集成在所述至少一个所述积分电容器上的装置;以及 在积分时间期间改变耦合到运算放大器的可变电阻器中的至少一个的电阻。

    Fabricated cylinder capacitor for a digital-to-analog converter
    5.
    发明授权
    Fabricated cylinder capacitor for a digital-to-analog converter 失效
    用于数模转换器的制造圆柱电容器

    公开(公告)号：US07473955B1

    公开(公告)日：2009-01-06

    申请号：US11371148

    申请日：2006-03-07

    申请人： Mehrdad Heshami ,  Mansour Keramat

    发明人： Mehrdad Heshami ,  Mansour Keramat

    IPC分类号： H01L29/94

    CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A fabricated cylinder capacitor having two or more layers is provided, each layer having a bottom plate and top plate portions. A first set of vias connect the bottom plate portions and a second set of vias connect the top plate portions. The bottom plate portions and the first set of vias comprise a bottom plate and the top plate portions and the second set of vias comprise a top plate of the capacitor. The layers may comprise five metal layers and may be produced using semiconductor fabrication methods. Also provided is a capacitor array having two or more cylinder capacitors where a set of connectors connect all top plates of the capacitors. The capacitor array may be used in a capacitive DAC, the capacitors being connected according to the architecture of the DAC. The capacitive DAC may be used in a SAR ADC.

    摘要翻译： 提供具有两层或更多层的制造的圆筒电容器，每层具有底板和顶板部分。 第一组通孔连接底板部分，第二组通孔连接顶板部分。 底板部分和第一组通孔包括底板，并且顶板部分和第二组通孔包括电容器的顶板。 这些层可以包括五个金属层，并且可以使用半导体制造方法制造。 还提供了具有两个或更多个气缸电容器的电容器阵列，其中一组连接器连接电容器的所有顶板。 电容器阵列可用于电容式DAC，电容器根据DAC的结构进行连接。 电容式DAC可用于SAR ADC。

    In-Situ Gain Calibration of Radio Frequency Devices Using Thermal Noise
    6.
    发明申请
    In-Situ Gain Calibration of Radio Frequency Devices Using Thermal Noise 有权
    使用热噪声的射频设备的现场增益校准

    公开(公告)号：US20080273637A1

    公开(公告)日：2008-11-06

    申请号：US12173166

    申请日：2008-07-15

    申请人： Timothy C. Kuo ,  Mansour Keramat ,  Edward Wai Yeung Liu

    发明人： Timothy C. Kuo ,  Mansour Keramat ,  Edward Wai Yeung Liu

    IPC分类号： H04L27/08

    CPC分类号： H04W52/367 ,  H04B17/0085 ,  H04B17/21 ,  H04W52/16 ,  H04W52/40

    摘要： An apparatus for calibrating gain of an radio frequency receiver (“Rx”) is disclosed to provide, among other things, a structure for performing in-situ gain calibration of an RF integrated circuit over time and/or over temperature without removing the RF integrated circuit from its operational configuration, especially when the gain of the RF integrated circuit is susceptible to variations in process, such as inherent with the CMOS process. In one embodiment, an exemplary apparatus includes a thermal noise generator configured to generate thermal noise as a calibrating signal into an input of an Rx path of an RF integrated circuit. The apparatus also includes a calibrator configured to first measure an output signal from an output of the Rx path, and then adjust a gain of the Rx path based on the thermal noise. In one embodiment, the thermal noise generator further includes a termination resistance and/or impedance.

    摘要翻译： 公开了一种用于校准射频接收机（“Rx”）的增益的装置，其特征在于提供一种用于在不消除RF集成的情况下随时间和/或过温度进行RF集成电路的原位增益校准的结构 特别是当RF集成电路的增益易受诸如CMOS工艺固有的工艺变化影响时。 在一个实施例中，示例性装置包括热噪声发生器，其被配置为产生作为校准信号的热噪声到RF集成电路的Rx路径的输入中。 该装置还包括校准器，其被配置为首先测量来自Rx路径的输出的输出信号，然后基于热噪声来调整Rx路径的增益。 在一个实施例中，热噪声发生器还包括端接电阻和/或阻抗。

    In-situ gain calibration of radio frequency devices using thermal noise
    9.
    发明授权
    In-situ gain calibration of radio frequency devices using thermal noise 有权
    使用热噪声的射频设备的原位增益校准

    公开(公告)号：US08428194B2

    公开(公告)日：2013-04-23

    申请号：US13399971

    申请日：2012-02-17

    申请人： Timothy C. Kuo ,  Mansour Keramat ,  Edward Wai Yeung Liu

    发明人： Timothy C. Kuo ,  Mansour Keramat ,  Edward Wai Yeung Liu

    IPC分类号： H03K9/00 ,  H04L27/00

    CPC分类号： H04W52/367 ,  H04B17/0085 ,  H04B17/21 ,  H04W52/16 ,  H04W52/40

    摘要： An apparatus for calibrating gain of an radio frequency receiver (“Rx”) is disclosed to provide, among other things, a structure for performing in-situ gain calibration of an RF integrated circuit over time and/or over temperature without removing the RF integrated circuit from its operational configuration, especially when the gain of the RF integrated circuit is susceptible to variations in process, such as inherent with the CMOS process. In one embodiment, an exemplary apparatus includes a thermal noise generator configured to generate thermal noise as a calibrating signal into an input of an Rx path of an RF integrated circuit. The apparatus also includes a calibrator configured to first measure an output signal from an output of the Rx path, and then adjust a gain of the Rx path based on the thermal noise. In one embodiment, the thermal noise generator further includes a termination resistance and/or impedance.

    摘要翻译： 公开了一种用于校准射频接收机（“Rx”）的增益的装置，其特征在于提供一种用于在不消除RF集成的情况下随时间和/或过温度进行RF集成电路的原位增益校准的结构 特别是当RF集成电路的增益易受诸如CMOS工艺固有的工艺变化影响时。 在一个实施例中，示例性装置包括热噪声发生器，其被配置为产生作为校准信号的热噪声到RF集成电路的Rx路径的输入中。 该装置还包括校准器，其被配置为首先测量来自Rx路径的输出的输出信号，然后基于热噪声来调整Rx路径的增益。 在一个实施例中，热噪声发生器还包括端接电阻和/或阻抗。

    Fabricated U-shaped capacitor for a digital-to-analog converter
    10.
    发明授权
    Fabricated U-shaped capacitor for a digital-to-analog converter 失效
    用于数模转换器的制造U形电容器

    公开(公告)号：US07456462B1

    公开(公告)日：2008-11-25

    申请号：US11371145

    申请日：2006-03-07

    申请人： Mehrdad Heshami ,  Mansour Keramat

    发明人： Mehrdad Heshami ,  Mansour Keramat

    IPC分类号： H01L29/94

    CPC分类号： H01L28/91 ,  H01L23/5223 ,  H01L28/87 ,  H01L2924/0002 ,  H03M1/468 ,  H03M1/804 ,  H01L2924/00

    摘要： A layered capacitor having top and bottom plates formed from multiple layers. The capacitor has a bottom layer comprising a bottom plate portion and at least one upper layer, each upper layer comprising top and bottom plate portions. A first set of vias connect the bottom plate portions and a second set of vias connect the top plate portions. The bottom plate portions and the first set of vias comprise a U-shaped bottom plate and the top plate portions and the second set of vias comprise a top plate of the capacitor device. The layers may comprise metal layers produced using semiconductor fabrication methods. Also provided is a capacitor array having two or more capacitors where connectors connect all top plate portions of the capacitors. The capacitor array may be used in a capacitive DAC, which may be used in a SAR ADC.

    摘要翻译： 具有由多层形成的顶板和底板的分层电容器。 电容器具有包括底板部分和至少一个上层的底层，每个上层包括顶板部分和底板部分。 第一组通孔连接底板部分，第二组通孔连接顶板部分。 底板部分和第一组通孔包括U形底板，并且顶板部分和第二组通孔包括电容器装置的顶板。 这些层可以包括使用半导体制造方法制造的金属层。 还提供了具有两个或更多个电容器的电容器阵列，其中连接器连接电容器的所有顶板部分。 电容器阵列可用于可用于SAR ADC的电容DAC。