Integrated Amplifier Circuit
    11.
    发明申请
    Integrated Amplifier Circuit 审中-公开
    集成放大器电路

    公开(公告)号:US20080272843A1

    公开(公告)日:2008-11-06

    申请号:US12115521

    申请日:2008-05-05

    IPC分类号: H03F3/45

    摘要: An integrated amplifier circuit is provided with an amplifier that is composed of at least two amplifier regions, the amplifier regions being arranged about a symmetry point, wherein each amplifier region has a plurality of transistors in a transistor region, and wherein transistors from different amplifier areas are arranged within the same transistor region. According to an aspect, provision is made that each amplifier region has at least two transistors. Whereby the integrated amplifier circuit can be used for semiconductor components

    摘要翻译: 集成放大器电路设置有由至少两个放大器区域组成的放大器,放大器区域围绕对称点布置,其中每个放大器区域在晶体管区域中具有多个晶体管,并且其中来自不同放大器区域的晶体管 被布置在相同的晶体管区域内。 根据一方面,提供每个放大器区域具有至少两个晶体管。 集成放大器电路可用于半导体元件

    Receiver, receiving method, and use of an in-phase signal and a quadrature-phase signal
    12.
    发明授权
    Receiver, receiving method, and use of an in-phase signal and a quadrature-phase signal 有权
    接收机,接收方式以及使用同相信号和正交相位信号

    公开(公告)号:US08755466B2

    公开(公告)日:2014-06-17

    申请号:US12358329

    申请日:2009-01-23

    IPC分类号: H03D3/22 H04B1/16 H04L7/06

    CPC分类号: H04B15/02

    摘要: A receiver, receiving method, and use of an in-phase signal and a quadrature-phase signal is provided, that includes a mixer in the receiving path, an oscillator whose output is connected to a mixer input of the mixer, whereby the oscillator is formed to output a base signal, oscillating at a base frequency, at the output, a clock generation device to generate a clock signal from the base signal, whose input is connected to the output of the oscillator, whereby the clock generation device has a frequency converter for converting a base frequency of the base signal by the factor F=x+A, where x is a positive whole number and A a rational number between 0 and 1, and a signal processing device, which is connected downstream of the mixer in the receive path, whereby the signal processing device is connected to the clock generation device for control with the clock signal.

    摘要翻译: 提供接收机,接收方法以及同相信号和正交相位信号的使用,其包括接收路径中的混频器,输出连接到混频器的混频器输入的振荡器,由此振荡器 形成为输出在基准频率在输出处振荡的基本信号,时钟发生装置,以从基本信号产生时钟信号,该基本信号的输入连接到振荡器的输出,由此时钟产生装置具有频率 转换器,用于将基本信号的基本频率转换为因子F = x + A,其中x是正整数,A是0和1之间的有理数,以及信号处理装置,其连接在混频器的下游 接收路径,由此信号处理装置连接到时钟发生装置,用于利用时钟信号进行控制。

    Circuit and Method for Image Frequency Rejection
    13.
    发明申请
    Circuit and Method for Image Frequency Rejection 有权
    图像频率抑制电路和方法

    公开(公告)号:US20140152370A1

    公开(公告)日:2014-06-05

    申请号:US14153295

    申请日:2014-01-13

    IPC分类号: H03D7/14

    CPC分类号: H03D7/1483 H04B1/28

    摘要: A circuit and method for image frequency rejection is provided that includes an analog dual-quadrature mixer device whose signal inputs for an in-phase-signal and a quadrature-phase signal are connected to an input circuit in the signal path and whose oscillator inputs for an in-phase oscillator signal and a quadrature-phase oscillator signal are connected to a local oscillator device, having an analog adder-amplifier device, which has a number of transistor pairs, in which in each case both transistors of each transistor pair are connected to the same load resistor for the addition of the signals applied at the control inputs of both transistors, and in which the control inputs of both transistors are connected downstream of the outputs of analog dual-quadrature mixer device, and having a multistage analog polyphase filter whose inputs are connected to outputs of the adder-amplifier device.

    摘要翻译: 提供了一种用于图像频率抑制的电路和方法,其包括模拟双正交混频器装置,其信号输入用于同相信号和正交相位信号连接到信号路径中的输入电路,并且其振荡器输入用于 同相振荡器信号和正交相位振荡器信号连接到具有多个晶体管对的模拟加法器 - 放大器装置的本地振荡器装置,其中在每种情况下,每个晶体管对的两个晶体管被连接 到相同的负载电阻器,用于增加施加在两个晶体管的控制输入端的信号,并且其中两个晶体管的控制输入连接在模拟双正交混频器装置的输出的下游,并具有多级模拟多相滤波器 其输入端连接到加法器 - 放大器装置的输出。

    CIRCUIT FOR A LOOP ANTENNA AND METHOD FOR TUNING
    14.
    发明申请
    CIRCUIT FOR A LOOP ANTENNA AND METHOD FOR TUNING 有权
    用于环路天线的电路和调谐方法

    公开(公告)号:US20100124890A1

    公开(公告)日:2010-05-20

    申请号:US12578919

    申请日:2009-10-14

    IPC分类号: H04B1/04

    CPC分类号: H04B1/0458 H01Q7/00

    摘要: A circuit for a loop antenna having a first antenna terminal and a second antenna terminal with an antenna impedance, and method for tuning an overall impedance that has an antenna impedance of a loop antenna and a tuning impedance, with an output amplifier for amplifying a transmit signal that has an output for connection to the first antenna terminal of the loop antenna, with a tuning device designed for automatic tuning that has a terminal, which is separated from the output of the output amplifier for connection to the second antenna terminal, in which the tuning device has an adjustable tuning impedance that is connected to the terminal, in which the tuning device has a measurement device that is connected to the tuning impedance in order to measure a voltage amplitude across the tuning impedance, in which the tuning device has a computing unit that is connected to the measurement device and the adjustable tuning impedance, and in which the computing unit is designed for automatic adjustment of the tuning impedance based on evaluation of the voltage amplitude and the tuning impedance.

    摘要翻译: 一种用于具有第一天线端子和具有天线阻抗的第二天线端子的环形天线的电路,以及用于调谐具有环形天线的天线阻抗的整体阻抗和调谐阻抗的方法,用于放大发送 信号,其具有用于连接到环形天线的第一天线端子的输出,具有被设计用于自动调谐的调谐装置,其具有与用于连接到第二天线端子的输出放大器的输出分离的端子,其中 调谐装置具有连接到端子的可调谐调谐阻抗,其中调谐装置具有连接到调谐阻抗的测量装置,以便测量跨越调谐阻抗的电压幅度,其中调谐装置具有 连接到测量装置的计算单元和可调谐调谐阻抗,并且其中计算单元被设计为自动的 基于电压幅度和调谐阻抗的评估来调整调谐阻抗。

    Phase-locked loop circuit
    15.
    发明授权
    Phase-locked loop circuit 有权
    锁相环电路

    公开(公告)号:US07120217B2

    公开(公告)日:2006-10-10

    申请号:US09971748

    申请日:2001-10-04

    IPC分类号: H04L12/50 H03L7/00 H03L7/06

    摘要: In a PLL circuit including a voltage-controlled oscillator, a phase detector and a final control element, the final control element contains two separate channels, between the phase detector and the voltage controlled oscillator, wherein one channel processes the useful signal components and the other channel processes the disturbance signal components of the synchronization pulses. Each channel has two tracks, for generation of a potential difference, wherein each track is connected to a capacitor plate.

    摘要翻译: 在包括压控振荡器,相位检测器和最终控制元件的PLL电路中,最终控制元件在相位检测器和压控振荡器之间包含两个单独的通道,其中一个通道处理有用信号分量,另一个通道 通道处理同步脉冲的干扰信号分量。 每个通道具有用于产生电势差的两个轨道,其中每个轨道连接到电容器板。