公开(公告)号：US07165018B2

公开(公告)日：2007-01-16

申请号：US10301887

申请日：2002-11-22

申请人： Jose L. Flores ,  Lewis Nardini ,  Maria B. H. Gill

发明人： Jose L. Flores ,  Lewis Nardini ,  Maria B. H. Gill

IPC分类号： G06F9/455

CPC分类号： G06F11/3648 ,  G01R31/31703 ,  G01R31/31705 ,  G06F11/3656

摘要： An memory access address comparator includes two comparators comparing an input memory access address with respective reference addresses. The comparators produce a match indication on selectable criteria, such as address size, full or partial overlap, greater than, less than, equal to, not equal to, less than or equal to, and greater than or equal to, and can be selectively chained. Input multiplexers permit memory access address bus selection. The comparator output may be selectively dependent upon corresponding data matches. The reference addresses, comparison data and control functions are enabled via central processing unit accessible memory mapped registers.

摘要翻译： 存储器访问地址比较器包括将输入存储器访问地址与相应的参考地址进行比较的两个比较器。 比较器根据可选择的标准产生匹配指示，例如地址大小，全部或部分重叠，大于，小于，等于，不等于，小于等于并且大于或等于，并且可以是选择性地 链接。 输入多路复用器允许存储器访问地址总线选择。 比较器输出可以选择性地依赖于相应的数据匹配。 参考地址，比较数据和控制功能通过中央处理单元可访问存储器映射寄存器使能。

公开(公告)号：US07117398B2

公开(公告)日：2006-10-03

申请号：US10302192

申请日：2002-11-22

申请人： Jose L. Flores ,  Lewis Nardini ,  Maria B. H. Gill

发明人： Jose L. Flores ,  Lewis Nardini ,  Maria B. H. Gill

IPC分类号： G06F11/30 ,  G06F7/02

CPC分类号： G06F11/3636 ,  G06F11/3656

摘要： An program counter address comparator includes two comparators comparing an input program counter address with respective reference addresses. The comparators produce a match indication on selectable criteria, such as greater than, less than, equal to, not equal to, less than or equal to, and greater than or equal to, and can be selectively chained. Input multiplexers permit selection of either the program counter address bus or a secondary address bus. The reference addresses and control functions are enabled via central processing unit accessible memory mapped registers.

公开(公告)号：US07610518B2

公开(公告)日：2009-10-27

申请号：US11467727

申请日：2006-08-28

申请人： Jose L. Flores ,  Lewis Nardini ,  Maria B. H. Gill

发明人： Jose L. Flores ,  Lewis Nardini ,  Maria B. H. Gill

IPC分类号： G06F11/00 ,  G06F11/30

CPC分类号： G06F11/3636 ,  G06F11/3656

摘要： An program counter address comparator includes two comparators comparing an input program counter address with respective reference addresses. The comparators produce a match indication on selectable criteria, such as greater than, less than, equal to, not equal to, less than or equal to, and greater than or equal to, and can be selectively chained. Input multiplexers permit selection of either the program counter address bus or a secondary address bus. The reference addresses and control functions are enabled via central processing unit accessible memory mapped registers.

摘要翻译： 程序计数器地址比较器包括将输入程序计数器地址与各个参考地址进行比较的两个比较器。 比较器产生可选标准的匹配指示，例如大于，小于，等于，不等于，小于或等于，且大于或等于，并且可以选择性地链接。 输入多路复用器允许选择程序计数器地址总线或辅助地址总线。 参考地址和控制功能通过中央处理单元可访问存储器映射寄存器使能。

公开(公告)号：US07457739B2

公开(公告)日：2008-11-25

申请号：US11467683

申请日：2006-08-28

申请人： Manisha Agarwala ,  Maria B. H. Gill

发明人： Manisha Agarwala ,  Maria B. H. Gill

IPC分类号： G06F9/455 ,  H03M7/00 ,  G06F11/00

CPC分类号： G06F11/3636 ,  G06F11/3656

摘要： A method of scheduling trace packets in an integrated circuit generating trace packets of plural types stores trace data in respective first-in-first-out buffers. If a timing trace data first-in-first-out buffer is empty, timing trace data packet is transmitted. If a program counter overall data first-in-first-out buffer is not empty and the processor is at a data interruptible boundary, a program counter data packet is transmitted. If data first-in-first-out buffer is not empty, a data packet is transmitted. The program counter data packets include program counter sync data, program counter exception data, program counter relative branch data and program counter absolute branch data.

摘要翻译： 一种在产生多种类型的跟踪分组的集成电路中调度跟踪分组的方法将跟踪数据存储在相应的先进先出缓冲器中。 如果定时跟踪数据先进先出缓冲器为空，则发送定时跟踪数据包。 如果程序计数器的总体数据先进先出缓冲器不为空并且处理器处于数据中断边界，则发送程序计数器数据分组。 如果数据先进先出缓冲器不为空，则传输数据包。 程序计数器数据包包括程序计数器同步数据，程序计数器异常数据，程序计数器相对分支数据和程序计数器绝对分支数据。

公开(公告)号：US07100151B2

公开(公告)日：2006-08-29

申请号：US10302024

申请日：2002-11-22

申请人： John M. Johnsen ,  Manisha Agarwala ,  Maria B. H. Gill

发明人： John M. Johnsen ,  Manisha Agarwala ,  Maria B. H. Gill

IPC分类号： G06F9/44

CPC分类号： G06F11/3636 ,  G06F11/3652

摘要： A method of tracing data processor activity with recover from detection of trace stream corruption. If the first trace data following detection of corruption is not a program counter sync point, then the trace transmits an indication of the current program counter address in an offset format from the program counter address of a last transmitted program counter sync point and then transmits trace data in event offset format. If the first trace data following detection of corruption is a program counter sync point, then the trace transmits trace data in event offset format.

公开(公告)号：US07047451B2

公开(公告)日：2006-05-16

申请号：US10302025

申请日：2002-11-22

申请人： Manisha Agarwala ,  Bryan Thome ,  John M. Johnsen ,  Gary L. Swoboda ,  Lewis Nardini ,  Maria B. H. Gill

发明人： Manisha Agarwala ,  Bryan Thome ,  John M. Johnsen ,  Gary L. Swoboda ,  Lewis Nardini ,  Maria B. H. Gill

IPC分类号： G06F11/00

CPC分类号： G06F11/3636 ,  G06F11/3656

摘要： A method of tracing program counter activity in a data processor periodically transmits a program counter sync point including the current program counter address. Between sync points the program counter address is indicated by a program counter offset relative to the last program counter sync point. The program counter offset is sent as integral number of sections of a predetermined number of bits. Program counter sync points are transmitted often enough so that the program counter offset requires at most one less section than the program counter address.

摘要翻译： 在数据处理器中跟踪程序计数器活动的方法周期性地发送包括当前程序计数器地址的程序计数器同步点。 在同步点之间，程序计数器地址由相对于最后一个程序计数器同步点的程序计数器偏移指示。 程序计数器偏移作为整数个预定位数的部分发送。 程序计数器的同步点经常被传送到足够多的程序计数器偏移量至少比程序计数器地址少一个部分。

公开(公告)号：US06272615B1

公开(公告)日：2001-08-07

申请号：US08851573

申请日：1997-05-02

申请人： Stephen (Hsiao Yi) Li ,  Jonathan Rowlands ,  Fuk Ho Pius Ng ,  Maria B. H. Gill

发明人： Stephen (Hsiao Yi) Li ,  Jonathan Rowlands ,  Fuk Ho Pius Ng ,  Maria B. H. Gill

IPC分类号： G06F1200

CPC分类号： G06F9/355 ,  G06F9/3004 ,  G06F9/30061 ,  G06F9/30167 ,  G06F9/322 ,  G06F9/325 ,  G06F9/345 ,  G06F9/35 ,  G06F9/383

摘要： A data processing device is provided with an indexed-immediate addressing mode for processing streams of data. An instruction register 900 receives an instruction for execution. Decoding circuitry 913 selects a register specified by a field in an instruction to provide an index value. An immediate field from the instruction is combined with the index value by multiplexor 910 to form an address which can be used to access a data value or to form a target address for a branch instruction. Mux control 915 parses the immediate value to determine how to combine the immediate value and the index value.

摘要翻译： 数据处理设备具有用于处理数据流的索引立即寻址模式。 指令寄存器900接收执行指令。 解码电路913选择由指令中的字段指定的寄存器以提供索引值。 来自指令的立即字段与索引值通过多路复用器910组合以形成可用于访问数据值或形成分支指令的目标地址的地址。 Mux控制915解析立即值，以确定如何组合立即值和索引值。