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    Semiconductor memory device
    12.
    发明申请
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US20060171238A1

    公开(公告)日：2006-08-03

    申请号：US11344206

    申请日：2006-02-01

    申请人： Mariko Iizuka

    发明人： Mariko Iizuka

    IPC分类号： G11C8/00

    CPC分类号： G11C11/4096 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C11/4076 ,  G11C2207/104

    摘要： A semiconductor memory device includes an interface unit connected to an external circuit, a data memory unit including a write data line, a read-out data line, a data control unit, and a memory block connected to the data control unit, and a read-out latch block connected between a read-out data line and the interface unit. The data control unit outputs data read out of the memory block to the read-out data line with a trailing edge of a clock being used as a trigger. The read-out latch block latches the data with a trailing edge of another clock, which is generated at least one cycle after the trailing edge of the aforementioned clock, being used as a trigger. The interface unit outputs the data to the external circuit with a leading edge of still another clock, which follows the aforementioned another clock, being used as a trigger.

    摘要翻译： 半导体存储器件包括连接到外部电路的接口单元，包括写入数据线，读出数据线，数据控制单元和连接到数据控制单元的存储块的数据存储单元，以及读取 - 连接在读出数据线和接口单元之间的锁存块。 数据控制单元将用于作为触发的时钟的后沿将从存储器块读出的数据输出到读出数据线。 读出锁存块用另一个时钟的后沿来锁存数据，该时钟在上述时钟的后沿之后至少一个周期被产生，作为触发。 接口单元将数据输出到外部电路，其中另一时钟的另一个时钟的前沿被跟随上述的另一时钟用作触发。

    SEMICONDUCTOR STORAGE DEVICE
    13.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE 有权
    半导体存储设备

    公开(公告)号：US20160197120A1

    公开(公告)日：2016-07-07

    申请号：US15048735

    申请日：2016-02-19

    申请人： Tadashi MIYAKAWA ,  Katsuhiko HOYA ,  Mariko IIZUKA ,  Takashi NAKAZAWA ,  Hiroyuki TAKENAKA

    发明人： Tadashi MIYAKAWA ,  Katsuhiko HOYA ,  Mariko IIZUKA ,  Takashi NAKAZAWA ,  Hiroyuki TAKENAKA

    IPC分类号： H01L27/22 ,  H01L43/08 ,  G11C11/16

    CPC分类号： H01L27/228 ,  G11C7/12 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0002 ,  H01L43/08

    摘要： A semiconductor storage device includes a cell array including resistance change elements formed above a semiconductor substrate; first cell transistors formed on the semiconductor substrate and provided in association with the resistance change elements; first gate electrodes included in the first cell transistor and extending in a first direction; a first bit lines electrically connected to the resistance change elements respectively and extending in a second direction perpendicular to the first direction; a second bit lines electrically connected to one end of a current path of the first cell transistors respectively and extending in the second direction; and first active areas in which the first cell transistors are formed, and which extend in a direction crossing the first direction at a first angle.

    摘要翻译： 一种半导体存储装置，包括：电池阵列，包括形成在半导体衬底上的电阻变化元件; 形成在半导体衬底上并与电阻变化元件相关联地设置的第一单元晶体管; 包括在第一单元晶体管中并沿第一方向延伸的第一栅电极; 分别电连接到所述电阻变化元件并沿垂直于所述第一方向的第二方向延伸的第一位线; 第二位线分别电连接到第一单元晶体管的电流路径的一端并沿第二方向延伸; 以及第一有源区，其中形成有第一单元晶体管，并且在与第一方向交叉的方向上以第一角度延伸。

    Semiconductor memory device and defective cell relieving method
    16.
    发明授权
    Semiconductor memory device and defective cell relieving method 有权
    半导体存储器件和有缺陷的电池释放方法

    公开(公告)号：US08837240B2

    公开(公告)日：2014-09-16

    申请号：US13618976

    申请日：2012-09-14

    申请人： Takayuki Iwai ,  Makoto Takahashi ,  Masaharu Wada ,  Mariko Iizuka ,  Kimimasa Imai

    发明人： Takayuki Iwai ,  Makoto Takahashi ,  Masaharu Wada ,  Mariko Iizuka ,  Kimimasa Imai

    IPC分类号： G11C7/00 ,  G11C29/00 ,  G11C29/04

    CPC分类号： G11C29/76 ,  G11C29/78 ,  G11C29/785 ,  G11C29/789 ,  G11C2029/0401 ,  G11C2229/743 ,  G11C2229/746

    摘要： A memory cell array of a first semiconductor chip includes a normal cell array and a spare cell array. A first defect address data storage circuit outputs first defect address data indicating an address of a defective memory cell in the memory cell array. A first comparison circuit compares address data with the first defect address data and outputs a first match signal in case of matching. A second defect address data storage circuit outputs second defect address data indicating an address of a defective memory cell in the memory cell array. A second comparison circuit compares the address data with the second defect address data and outputs a second match signal in case of matching.

    摘要翻译： 第一半导体芯片的存储单元阵列包括正常单元阵列和备用单元阵列。 第一缺陷地址数据存储电路输出表示存储单元阵列中的有缺陷的存储单元的地址的第一缺陷地址数据。 第一比较电路将地址数据与第一缺陷地址数据进行比较，并在匹配的情况下输出第一匹配信号。 第二缺陷地址数据存储电路输出指示存储单元阵列中缺陷存储单元地址的第二缺陷地址数据。 第二比较电路将地址数据与第二缺陷地址数据进行比较，并在匹配的情况下输出第二匹配信号。

    Synchronous type semiconductor storage device and DRAM
    17.
    发明授权
    Synchronous type semiconductor storage device and DRAM 有权
    同步型半导体存储器件和DRAM

    公开(公告)号：US08625384B2

    公开(公告)日：2014-01-07

    申请号：US13053357

    申请日：2011-03-22

    申请人： Mariko Iizuka

    发明人： Mariko Iizuka

    IPC分类号： G11C8/00

    CPC分类号： G11C11/4076 ,  G11C7/1096 ,  G11C11/4091

    摘要： A synchronous type semiconductor storage device includes an array unit which includes a cell array and sense amplifiers. The synchronous type semiconductor storage device includes a read/write pulse generator which generates a read pulse signal and a write pulse signal according to a clock signal, the clock signal defining one cycle time of a read operation and a write operation with respect to the array unit as one cycle. The synchronous type semiconductor storage device includes a secondary amplifier which is activated according to the read pulse signal to read out data stored in the sense amplifiers through the read/write line. The synchronous type semiconductor storage device includes a write driver which is activated according to the write pulse signal to write data in the sense amplifiers through the read/write line.

    摘要翻译： 同步型半导体存储装置包括具有单元阵列和读出放大器的阵列单元。 同步型半导体存储装置包括读/写脉冲发生器，其根据时钟信号产生读脉冲信号和写脉冲信号，时钟信号定义读操作的一个周期时间和相对于阵列的写操作 单位为一个周期。 同步型半导体存储装置包括根据读取脉冲信号而被激活的次级放大器，以通过读/写线读出存储在读出放大器中的数据。 同步型半导体存储装置包括写入驱动器，该写入驱动器根据写入脉冲信号被激活，以通过读取/写入线在读出放大器中写入数据。

    SEMICONDUCTOR MEMORY DEVICE AND DEFECTIVE CELL RELIEVING METHOD
    18.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND DEFECTIVE CELL RELIEVING METHOD 有权
    半导体存储器件和缺陷细胞消除方法

    公开(公告)号：US20130077420A1

    公开(公告)日：2013-03-28

    申请号：US13618976

    申请日：2012-09-14

    申请人： Takayuki Iwai ,  Makoto Takahashi ,  Masaharu Wada ,  Mariko Iizuka ,  Kimimasa Imai

    发明人： Takayuki Iwai ,  Makoto Takahashi ,  Masaharu Wada ,  Mariko Iizuka ,  Kimimasa Imai

    IPC分类号： G11C29/00

    CPC分类号： G11C29/76 ,  G11C29/78 ,  G11C29/785 ,  G11C29/789 ,  G11C2029/0401 ,  G11C2229/743 ,  G11C2229/746

    摘要： A memory cell array of a first semiconductor chip includes a normal cell array and a spare cell array. A first defect address data storage circuit outputs first defect address data indicating an address of a defective memory cell in the memory cell array. A first comparison circuit compares address data with the first defect address data and outputs a first match signal in case of matching. A second defect address data storage circuit outputs second defect address data indicating an address of a defective memory cell in the memory cell array. A second comparison circuit compares the address data with the second defect address data and outputs a second match signal in case of matching.

    摘要翻译： 第一半导体芯片的存储单元阵列包括正常单元阵列和备用单元阵列。 第一缺陷地址数据存储电路输出表示存储单元阵列中的有缺陷的存储单元的地址的第一缺陷地址数据。 第一比较电路将地址数据与第一缺陷地址数据进行比较，并在匹配的情况下输出第一匹配信号。 第二缺陷地址数据存储电路输出指示存储单元阵列中缺陷存储单元地址的第二缺陷地址数据。 第二比较电路将地址数据与第二缺陷地址数据进行比较，并在匹配的情况下输出第二匹配信号。

    SEMICONDUCTOR INTEGRATED CIRCUIT
    19.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
    半导体集成电路

    公开(公告)号：US20110267108A1

    公开(公告)日：2011-11-03

    申请号：US13185655

    申请日：2011-07-19

    申请人： Mariko IIZUKA

    发明人： Mariko IIZUKA

    IPC分类号： H03K5/00

    CPC分类号： H03K5/1565 ,  G06F1/04 ,  G06F1/10 ,  H03K5/1506

    摘要： A first counter detects a rising edge of a clock signal, and generates a first signal having a multiplied cycle of the clock signal. A second counter detects a falling edge of the clock signal, and generates a second signal having a multiplied cycle of the clock signal. A first line transfers the first signal, while a second line transfers the second signal. A phase comparator is connected to the first line and the second line to generate a third signal based on a phase difference between the first signal and the second signal and output the third signal to one of the circuit units. A plurality of the phase comparators are connected to the first line and the second line, and are disposed between one of the ends of the first line and the second line and one of the circuit units.

    摘要翻译： 第一计数器检测时钟信号的上升沿，并产生具有时钟信号相乘周期的第一信号。 第二计数器检测时钟信号的下降沿，并产生具有时钟信号相乘周期的第二信号。 第一行传送第一信号，而第二行传送第二信号。 相位比较器连接到第一线路和第二线路，以基于第一信号和第二信号之间的相位差产生第三信号，并将第三信号输出到电路单元之一。 多个相位比较器连接到第一线和第二线，并且被布置在第一线和第二线的一端之间以及一个电路单元中。

    Semiconductor integrated circuit
    20.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US08008946B2

    公开(公告)日：2011-08-30

    申请号：US12533573

    申请日：2009-07-31

    申请人： Mariko Iizuka

    发明人： Mariko Iizuka

    IPC分类号： G01R25/00 ,  H03D13/00

    CPC分类号： H03K5/1565 ,  G06F1/04 ,  G06F1/10 ,  H03K5/1506

    摘要： A first counter detects a rising edge of a clock signal, and generates a first signal having a multiplied cycle of the clock signal.A second counter detects a falling edge of the clock signal, and generates a second signal having a multiplied cycle of the clock signal. A first line transfers the first signal, while a second line transfers the second signal. A phase comparator is connected to the first line and the second line to generate a third signal based on a phase difference between the first signal and the second signal and output the third signal to one of the circuit units.A plurality of the phase comparators are connected to the first line and the second line, and are disposed between one of the ends of the first line and the second line and one of the circuit units.

    摘要翻译： 第一计数器检测时钟信号的上升沿，并产生具有时钟信号相乘周期的第一信号。 第二计数器检测时钟信号的下降沿，并产生具有时钟信号相乘周期的第二信号。 第一行传送第一信号，而第二行传送第二信号。 相位比较器连接到第一线路和第二线路，以基于第一信号和第二信号之间的相位差产生第三信号，并将第三信号输出到电路单元之一。 多个相位比较器连接到第一线和第二线，并且被布置在第一线和第二线的一端之间以及一个电路单元中。