公开(公告)号：US08185854B1

公开(公告)日：2012-05-22

申请号：US12544970

申请日：2009-08-20

Applicant: Michael D. Hutton ,  Jason Govig

Inventor： Michael D. Hutton ,  Jason Govig

IPC: G06F17/50

CPC classification number: G06F17/5031

Abstract: A method for designing a system on a target device is disclosed. Domains and sub-domains in the system are identified. A sub-domain is divided into a plurality of chunks. Slacks for the chunks are computed in parallel. Other embodiments are described and claimed.

Abstract translation: 公开了一种在目标设备上设计系统的方法。 识别系统中的域和子域。 子域被分成多个块。 块的松弛计算并行计算。 描述和要求保护其他实施例。

公开(公告)号：US07818705B1

公开(公告)日：2010-10-19

申请号：US11102069

申请日：2005-04-08

Applicant: Michael D. Hutton ,  David Lewis

Inventor： Michael D. Hutton ,  David Lewis

IPC: G06F17/50

CPC classification number: G06F17/5027 ,  G06F17/5054 ,  G06F2217/62

Abstract: A skew generator unit includes a delay chain. The delay chain is coupled to a clock line that transmits a clock signal. The delay chain generates a skewed clock signal having a unit of delay from the clock signal. The skew generator unit also includes a selector. The selector is coupled to the delay chain and the clock line and may select one of the clock signal and the skewed clock signal.

Abstract translation: 偏斜发生器单元包括延迟链。 延迟链耦合到发送时钟信号的时钟线。 延迟链产生具有来自时钟信号的延迟单位的偏斜时钟信号。 偏斜发生器单元还包括选择器。 选择器耦合到延迟链和时钟线，并且可以选择时钟信号和偏斜时钟信号之一。

公开(公告)号：US07812635B1

公开(公告)日：2010-10-12

申请号：US11430370

申请日：2006-05-08

Applicant: Michael D. Hutton

Inventor： Michael D. Hutton

IPC: H03K19/177 ,  H03K17/62

CPC classification number: H03K19/17736 ,  H03K19/17728

Abstract: A high efficiency PLD architecture having adjacent logic elements that can be selectively combined to perform higher order logic functions than can be performed alone by a single logic element. The programmable logic device includes a logic block having a first logic element including a first look up table. The first look up table includes a first pair of sub-function generators and is capable of implementing logic functions of a first order. The logic block also includes a second logic element having a second input look up table including a second pair of sub-function generators. Programmable sharing circuitry is also included in the logic block. The programmable sharing circuitry selectively couples the first pair of sub-function generators and the second pair of sub-function generators so that the first logic element is capable of performing logic functions of either (i) the first order, or (ii) a second order, wherein the second order is higher than the first order.

Abstract translation: 具有相邻逻辑元件的高效率PLD架构，其可以被选择性地组合以执行比单个逻辑元件单独执行的更高阶逻辑功能。 可编程逻辑器件包括具有包括第一查询表的第一逻辑元件的逻辑块。 第一查询表包括第一对子功能发生器，并且能够实现一阶的逻辑功能。 逻辑块还包括具有包括第二对子功能发生器的第二输入查找表的第二逻辑元件。 可编程共享电路也包含在逻辑块中。 可编程共享电路选择性地耦合第一对子功能发生器和第二对子功能发生器，使得第一逻辑元件能够执行（i）第一阶或（ii）第二逻辑单元的逻辑功能， 其中第二级高于第一级。

公开(公告)号：US07733124B1

公开(公告)日：2010-06-08

申请号：US11766817

申请日：2007-06-22

Applicant: Keith Duwel ,  Michael D. Hutton

Inventor： Keith Duwel ,  Michael D. Hutton

IPC: H03K19/177

CPC classification number: H03K19/17728

Abstract: A programmable logic device (PLD) includes a core region having a plurality of logical array blocks (LABs). Each one of the plurality of logical array blocks include a plurality of logic elements capable of communicating with each other through interconnections defined within each logical array block. The logic elements include a look up table (LUT), wherein a LUT of a first logic element and a LUT of a second logic element share a register. In one embodiment, more than two logic elements may share a register. Thus, the embodiments provide for the ability to vary sequential logic, e.g., registers, instead of rigidly fixing the sequential logic and consequently the ratio of combinatorial logic to sequential logic.

Abstract translation: 可编程逻辑器件（PLD）包括具有多个逻辑阵列块（LAB）的核心区域。 多个逻辑阵列块中的每一个包括能够通过在每个逻辑阵列块内定义的互连而彼此通信的多个逻辑元件。 逻辑元件包括查找表（LUT），其中第一逻辑元件的LUT和第二逻辑元件的LUT共享寄存器。 在一个实施例中，多于两个逻辑元件可以共享寄存器。 因此，这些实施例提供了改变顺序逻辑（例如，寄存器）的能力，而不是刚性地固定顺序逻辑，并且因此改变组合逻辑与顺序逻辑的比率。

公开(公告)号：US07675319B2

公开(公告)日：2010-03-09

申请号：US12125824

申请日：2008-05-22

Applicant: Michael D. Hutton

Inventor： Michael D. Hutton

IPC: H03K19/173

CPC classification number: H03K19/17728

Abstract: A CLB-based PLD with logic cells having improved logic, register, arithmetic, logic packing and timing functions and capabilities is disclosed. The CLBs of the PLD are arranged in rows and columns of an array and are interconnect by a plurality of interconnect lines. Each of the plurality of CLBs has a first slice of logic cells and a second slice of logic cells arranged in a first column and a second column. First and second carry chains are provided between each of the logic cells of each column. At least one of the logic cells includes one or more Look Up Tables for implanting logic functions on a set of inputs provided to the one logic cell and an arithmetic logic circuit configured to receive a carry-in signal and to generate a carry-out signal forming part of the first carry chain. In one embodiment, the logic cell further includes a first output register and a second output register and the set of outputs generated by the logic cell are partitioned among the first output register and the second output register. In another embodiment, an output of one of the registers is provided as an input to one of the Look Up Tables of the cell through a register feedback connection. In yet another embodiment, the set of inputs provided to a first and a second of the Look Up Tables are different, enabling a higher degree of logic efficiency or “packing” by enabling each cell to perform logic functions on two different sets of inputs as opposed to only the same set of inputs. Finally, in another embodiment, the arithmetic logic circuit is capable of generating two SUM output signals.

Abstract translation: 公开了具有逻辑单元的具有改进的逻辑，寄存器，算术，逻辑封装和定时功能和能力的基于CLB的PLD。 PLD的CLB被布置成阵列的行和列，并且通过多条互连线互连。 多个CLB中的每一个具有布置在第一列和第二列中的逻辑单元的第一切片和逻辑单元的第二切片。 在每列的每个逻辑单元之间提供第一和第二进位链。 逻辑单元中的至少一个包括用于在提供给一个逻辑单元的一组输入上植入逻辑功能的一个或多个查找表和被配置为接收进位信号并产生进位输出信号的算术逻辑电路 形成第一个进位链的一部分。 在一个实施例中，逻辑单元还包括第一输出寄存器和第二输出寄存器，并且逻辑单元产生的输出集合在第一输出寄存器和第二输出寄存器之间被分区。 在另一实施例中，寄存器之一的输出通过寄存器反馈连接被提供作为单元的查找表之一的输入。 在另一个实施例中，提供给第一和第二查找表的输入组是不同的，通过使每个单元能够在两组不同的输入集上执行逻辑功能，能够实现更高程度的逻辑效率或“打包”，如 反对只有同一组投入。 最后，在另一个实施例中，算术逻辑电路能够产生两个SUM输出信号。

公开(公告)号：US20090271465A1

公开(公告)日：2009-10-29

申请号：US12111156

申请日：2008-04-28

Applicant: Erhard Joachim Pistorius ,  Michael D. Hutton

Inventor： Erhard Joachim Pistorius ,  Michael D. Hutton

IPC: G06F7/485

CPC classification number: G06F17/10 ,  G06F7/507 ,  G06F7/508

Abstract: Hybrid adder circuitry is provided for integrated circuits such as programmable integrated circuits. The hybrid adder may combine the capabilities of multiple adder architectures. Hybrid adders may include carry select and carry ripple adder circuits. The adder circuits may be combined using a carry look-ahead architecture. Adder functionality may be implemented using the resources of logic regions on the programmable integrated circuits. Each logic region may include combinatorial logic such as look-up table logic and register circuitry. The hybrid adder circuitry may receive input words to be added from the combinatorial circuitry and may produce corresponding arithmetic sum output signals to the register circuitry.

Abstract translation: 为诸如可编程集成电路的集成电路提供混合加法器电路。 混合加法器可以组合多个加法器架构的能力。 混合加法器可以包括进位选择和进位纹波加法器电路。 加法器电路可以使用携带查找结构来组合。 可以使用可编程集成电路上的逻辑区域的资源来实现加法器功能。 每个逻辑区域可以包括诸如查找表逻辑和寄存器电路的组合逻辑。 混合加法器电路可以从组合电路接收要添加的输入字，并且可以向寄存器电路产生相应的算术和输出信号。

公开(公告)号：US07312633B1

公开(公告)日：2007-12-25

申请号：US11550218

申请日：2006-10-17

Applicant: Michael D. Hutton ,  David Lewis

Inventor： Michael D. Hutton ,  David Lewis

IPC: H01L25/00 ,  H03K19/177 ,  H03K19/173 ,  G06F7/38

CPC classification number: H01L27/11898 ,  H01L27/0207 ,  H03K19/17744

Abstract: Techniques are provided for routing signals to and from input/output pads on a programmable chip that reduce signal delay times. A programmable routing structure is provided that is dedicated to routing signals to and from the input/output (I/O) pads. The programmable routing structure can include long conductors that transmit signals across the chip quickly without the delay encountered in shorter routing conductors. Signals can be routed to and from the I/O pads through vertical and horizontal dedicated routing conductors that bypass global routing conductors. The dedicated I/O routing structure allows signals to be driven onto the chip and off chip more quickly can be achieved through standard programmable routing structures. The dedicated I/O routing structure can be depopulated to reduce the number of programmable connections between the individual conductors, decreasing die area requirements.

Abstract translation: 提供技术用于将信号路由到可编程芯片上的输入/输出焊盘上，以减少信号延迟时间。 提供了可编程路由结构，其专用于将信号路由到输入/输出（I / O）焊盘。 可编程路由结构可以包括长导体，其在芯片上快速传输信号，而不会在较短路由导体中遇到延迟。 信号可以通过垂直和水平专用路由导线从I / O焊盘传送，从而绕过全局布线导线。 专用I / O路由结构允许通过标准可编程路由结构实现信号更快地驱动到芯片和芯片上。 可以减少专用I / O路由结构，以减少单个导体之间的可编程连接数量，从而减少管芯面积要求。

公开(公告)号：US09165931B1

公开(公告)日：2015-10-20

申请号：US14187185

申请日：2014-02-21

Applicant: Herman Schmit ,  David Lewis ,  Michael D. Hutton ,  Dana How ,  Andy L. Lee

Inventor： Herman Schmit ,  David Lewis ,  Michael D. Hutton ,  Dana How ,  Andy L. Lee

IPC: H01L27/115 ,  G06F17/50 ,  H01L27/105

CPC classification number: G06F17/5054 ,  G06F15/7867 ,  H01L27/115 ,  H03K19/17728

Abstract: An integrated circuit (IC) includes a substrate that is common to the IC and variants of the IC. The IC also includes a first set of interconnect layers fabricated above the substrate. The first set of interconnect layers is used to couple programmable interconnect of the IC to a first circuit in the substrate. The IC further includes a second set of interconnect layers fabricated above the substrate. The second set of interconnect layers is used to differentiate features of the IC from variants of the IC by selectively coupling the programmable interconnect to a second circuit in the substrate.

Abstract translation: 集成电路（IC）包括IC的通用基板和IC的变体。 IC还包括在衬底上方制造的第一组互连层。 第一组互连层用于将IC的可编程互连件耦合到衬底中的第一电路。 IC还包括在衬底上方制造的第二组互连层。 第二组互连层用于通过选择性地将可编程互连连接到衬底中的第二电路来区分IC的特征与IC的变体。

公开(公告)号：US08521801B2

公开(公告)日：2013-08-27

申请号：US12111156

申请日：2008-04-28

Applicant: Erhard Joachim Pistorius ,  Michael D. Hutton

Inventor： Erhard Joachim Pistorius ,  Michael D. Hutton

IPC: G06F7/50

CPC classification number: G06F17/10 ,  G06F7/507 ,  G06F7/508

Abstract: Hybrid adder circuitry is provided for integrated circuits such as programmable integrated circuits. The hybrid adder may combine the capabilities of multiple adder architectures. Hybrid adders may include carry select and carry ripple adder circuits. The adder circuits may be combined using a carry look-ahead architecture. Adder functionality may be implemented using the resources of logic regions on the programmable integrated circuits. Each logic region may include combinatorial logic such as look-up table logic and register circuitry. The hybrid adder circuitry may receive input words to be added from the combinatorial circuitry and may produce corresponding arithmetic sum output signals to the register circuitry.

Abstract translation: 为诸如可编程集成电路的集成电路提供混合加法器电路。 混合加法器可以组合多个加法器架构的能力。 混合加法器可以包括进位选择和进位纹波加法器电路。 加法器电路可以使用携带查找结构来组合。 可以使用可编程集成电路上的逻辑区域的资源来实现加法器功能。 每个逻辑区域可以包括诸如查找表逻辑和寄存器电路的组合逻辑。 混合加法器电路可以从组合电路接收要添加的输入字，并且可以向寄存器电路产生相应的算术和输出信号。

公开(公告)号：US08519740B2

公开(公告)日：2013-08-27

申请号：US13345564

申请日：2012-01-06

Applicant: Michael D. Hutton ,  David Lewis

Inventor： Michael D. Hutton ,  David Lewis

IPC: H03K19/173

CPC classification number: H03K19/17764 ,  H03K19/17736

Abstract: An integrated circuit may include programmable logic regions coupled in parallel to an interconnect bus. Multiplexing circuitry may be interposed between the programmable logic regions and the interconnect bus. The multiplexing circuitry may be formed from multiplexing circuits formed in a cascade structure. The multiplexing circuitry may dynamically receive control signals that determines which programmable logic region is allowed to drive output signals onto the interconnect bus. Alternatively, each programmable logic region may have an associated output circuit that is coupled to the interconnect bus. The output circuits may be dynamically controlled by control circuitry. The output circuits may receive control signals from the control circuitry that selectively enable and selectively disable the output circuits. The output circuits may be formed with logic circuitry that ensures that the interconnect bus is not simultaneously driven by the output circuits.

Abstract translation: 集成电路可以包括与互连总线并联耦合的可编程逻辑区域。 多路复用电路可以插在可编程逻辑区和互连总线之间。 复用电路可以由级联结构中形成的多路复用电路形成。 复用电路可以动态地接收控制信号，该控制信号确定允许哪个可编程逻辑区域将输出信号驱动到互连总线上。 或者，每个可编程逻辑区域可以具有耦合到互连总线的相关联的输出电路。 输出电路可以由控制电路动态控制。 输出电路可以接收来自控制电路的控制信号，其选择性地启用和选择性地禁用输出电路。 输出电路可以由确保互连总线不由输出电路同时驱动的逻辑电路形成。