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    Apparatus for field-programmable gate array with configurable architecture and associated methods
    1.
    发明授权
    Apparatus for field-programmable gate array with configurable architecture and associated methods 有权
    具有可配置架构和相关方法的现场可编程门阵列的装置

    公开(公告)号：US09165931B1

    公开(公告)日：2015-10-20

    申请号：US14187185

    申请日：2014-02-21

    申请人： Herman Schmit ,  David Lewis ,  Michael D. Hutton ,  Dana How ,  Andy L. Lee

    发明人： Herman Schmit ,  David Lewis ,  Michael D. Hutton ,  Dana How ,  Andy L. Lee

    IPC分类号： H01L27/115 ,  G06F17/50 ,  H01L27/105

    CPC分类号： G06F17/5054 ,  G06F15/7867 ,  H01L27/115 ,  H03K19/17728

    摘要： An integrated circuit (IC) includes a substrate that is common to the IC and variants of the IC. The IC also includes a first set of interconnect layers fabricated above the substrate. The first set of interconnect layers is used to couple programmable interconnect of the IC to a first circuit in the substrate. The IC further includes a second set of interconnect layers fabricated above the substrate. The second set of interconnect layers is used to differentiate features of the IC from variants of the IC by selectively coupling the programmable interconnect to a second circuit in the substrate.

    摘要翻译： 集成电路（IC）包括IC的通用基板和IC的变体。 IC还包括在衬底上方制造的第一组互连层。 第一组互连层用于将IC的可编程互连件耦合到衬底中的第一电路。 IC还包括在衬底上方制造的第二组互连层。 第二组互连层用于通过选择性地将可编程互连连接到衬底中的第二电路来区分IC的特征与IC的变体。

    User-Accessible Freeze-Logic for Dynamic Power Reduction and Associated Methods
    2.
    发明申请
    User-Accessible Freeze-Logic for Dynamic Power Reduction and Associated Methods 有权
    用户可访问的冻结逻辑用于动态功率降低和相关方法

    公开(公告)号：US20100026340A1

    公开(公告)日：2010-02-04

    申请号：US12577061

    申请日：2009-10-09

    申请人： Michael D. Hutton ,  Andy L. Lee

    发明人： Michael D. Hutton ,  Andy L. Lee

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17748 ,  H03K19/17784

    摘要： A programmable logic device (PLD) includes a configuration circuit, and first and second freeze-logic circuits. The configuration circuit provides configuration data for configuring programmable resources of the PLD during a configuration mode of the PLD. One of the two freeze-logic circuits provides a freeze logic signal during the configuration mode of the PLD. The other freeze-logic circuit provides a freeze logic signal during a user mode of the PLD.

    摘要翻译： 可编程逻辑器件（PLD）包括配置电路以及第一和第二冻结逻辑电路。 配置电路提供用于在PLD的配置模式期间配置PLD的可编程资源的配置数据。 两个冻结逻辑电路之一在PLD的配置模式期间提供冻结逻辑信号。 另一个冻结逻辑电路在PLD的用户模式期间提供冻结逻辑信号。

    User-accessible freeze-logic for dynamic power reduction and associated methods
    3.
    发明授权
    User-accessible freeze-logic for dynamic power reduction and associated methods 有权
    用户可访问的冻结逻辑，用于动态功率降低和相关方法

    公开(公告)号：US07605603B1

    公开(公告)日：2009-10-20

    申请号：US12040100

    申请日：2008-02-29

    申请人： Michael D. Hutton ,  Andy L. Lee

    发明人： Michael D. Hutton ,  Andy L. Lee

    IPC分类号： H03K19/173

    CPC分类号： H03K19/17748 ,  H03K19/17784

    摘要： A programmable logic device (PLD) includes a configuration circuit, and first and second freeze-logic circuits. The configuration circuit provides configuration data for configuring programmable resources of the PLD during a configuration mode of the PLD. One of the two freeze-logic circuits provides a freeze logic signal during the configuration mode of the PLD. The other freeze-logic circuit provides a freeze logic signal during a user mode of the PLD.

    摘要翻译： 可编程逻辑器件（PLD）包括配置电路以及第一和第二冻结逻辑电路。 配置电路提供用于在PLD的配置模式期间配置PLD的可编程资源的配置数据。 两个冻结逻辑电路之一在PLD的配置模式期间提供冻结逻辑信号。 另一个冻结逻辑电路在PLD的用户模式期间提供冻结逻辑信号。

    User-accessible freeze-logic for dynamic power reduction and associated methods
    4.
    发明授权
    User-accessible freeze-logic for dynamic power reduction and associated methods 有权
    用户可访问的冻结逻辑，用于动态功率降低和相关方法

    公开(公告)号：US07839165B2

    公开(公告)日：2010-11-23

    申请号：US12577061

    申请日：2009-10-09

    申请人： Michael D. Hutton ,  Andy L. Lee

    发明人： Michael D. Hutton ,  Andy L. Lee

    IPC分类号： H03K19/173

    CPC分类号： H03K19/17748 ,  H03K19/17784

    摘要： A programmable logic device (PLD) includes a configuration circuit, and first and second freeze-logic circuits. The configuration circuit provides configuration data for configuring programmable resources of the PLD during a configuration mode of the PLD. One of the two freeze-logic circuits provides a freeze logic signal during the configuration mode of the PLD. The other freeze-logic circuit provides a freeze logic signal during a user mode of the PLD.

    摘要翻译： 可编程逻辑器件（PLD）包括配置电路以及第一和第二冻结逻辑电路。 配置电路提供用于在PLD的配置模式期间配置PLD的可编程资源的配置数据。 两个冻结逻辑电路之一在PLD的配置模式期间提供冻结逻辑信号。 另一个冻结逻辑电路在PLD的用户模式期间提供冻结逻辑信号。

    Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers
    5.
    发明授权
    Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers 失效
    可编程逻辑器件具有具有专用硬件的逻辑元件，以将查找表配置为寄存器

    公开(公告)号：US07705628B1

    公开(公告)日：2010-04-27

    申请号：US11486164

    申请日：2006-07-12

    申请人： Michael D. Hutton ,  Andy L. Lee ,  Gregg William Baeckler ,  Jinyong Yuan ,  Keith Duwel

    发明人： Michael D. Hutton ,  Andy L. Lee ,  Gregg William Baeckler ,  Jinyong Yuan ,  Keith Duwel

    IPC分类号： G06F7/38 ,  H03K19/173 ,  H03K19/177 ,  H03K19/094 ,  H01L25/00

    CPC分类号： H03K19/173 ,  H03K19/1736 ,  H03K19/17728

    摘要： A programmable logic device architecture having logic elements with dedicated hardware to configure the look up tables of the logic element to either perform logic functions or to operate as a register for pipelining or other purposes. The programmable logic device includes a general interconnect and a plurality of logic array blocks interconnected by the general interconnect. Each of the plurality of logic blocks further includes one or more logic elements. The logic elements each include a first look up table, a second look up table, and dedicated hardware within the logic element to configure the first look table and the second look up table as a register without having to use the general interconnect. In one embodiment, the dedicated hardware includes a plurality of dedicated interconnects within the logic element to configure the two look up tables as a pair of cross coupled muxes or latches when configured as a register.

    摘要翻译： 具有逻辑元件的可编程逻辑器件结构具有专用硬件以配置逻辑元件的查找表以执行逻辑功能或作为流水线或其它目的的寄存器来操作。 可编程逻辑器件包括通用互连和通过一般互连互连的多个逻辑阵列块。 多个逻辑块中的每一个还包括一个或多个逻辑元件。 逻辑元件各自包括第一查询表，第二查询表和逻辑元件内的专用硬件，以将第一查询表和第二查询表配置为寄存器而不必使用通用互连。 在一个实施例中，专用硬件包括逻辑元件内的多个专用互连，以在配置为寄存器时将两个查找表配置为一对交叉耦合的多路复用器或锁存器。

    Apparatus and method for the arithmetic over-ride of look up table outputs in a programmable logic device
    6.
    发明授权
    Apparatus and method for the arithmetic over-ride of look up table outputs in a programmable logic device 有权
    用于在可编程逻辑器件中查询表输出的算术覆盖的装置和方法

    公开(公告)号：US07812633B1

    公开(公告)日：2010-10-12

    申请号：US11584308

    申请日：2006-10-20

    申请人： Andy L. Lee ,  David Lewis ,  Philip Pan ,  James G. Schleicher, II

    发明人： Andy L. Lee ,  David Lewis ,  Philip Pan ,  James G. Schleicher, II

    IPC分类号： H03K19/173 ,  H01L25/00

    CPC分类号： H03K19/17728

    摘要： A programmable logic device having a Logic Element with an N-stage Look Up Table (LUT), dedicated hardware for performing a non-LUT logic function, and an over-ride element configured to selectively force a muxing stage within the N-stage LUT to select either one or more LUT configuration bit inputs or the output of the non-LUT logic function as the output of the LUT. In various embodiments, the non-LUT functions can include addition, subtraction, multiplication, division, digital signal processing, memory storage, etc.

    摘要翻译： 具有具有N级查找表（LUT）的逻辑元件，用于执行非LUT逻辑功能的专用硬件的可编程逻辑器件以及被配置为选择性地迫使N级LUT内的多路复用级的过载元件 选择一个或多个LUT配置位输入或非LUT逻辑功能的输出作为LUT的输出。 在各种实施例中，非LUT功能可以包括加法，减法，乘法，除法，数字信号处理，存储器存储等

    Structures for LUT-based arithmetic in PLDs
    8.
    发明授权
    Structures for LUT-based arithmetic in PLDs 有权
    在PLD中基于LUT的算术的结构

    公开(公告)号：US07558812B1

    公开(公告)日：2009-07-07

    申请号：US10723104

    申请日：2003-11-26

    申请人： Ketan Padalia ,  David Cashman ,  David Lewis ,  Andy L. Lee ,  Jay Schleicher ,  Jinyong Yuan ,  Henry Kim

    发明人： Ketan Padalia ,  David Cashman ,  David Lewis ,  Andy L. Lee ,  Jay Schleicher ,  Jinyong Yuan ,  Henry Kim

    IPC分类号： G06F7/38

    CPC分类号： G06F7/575 ,  H03K19/177 ,  H03K19/17728

    摘要： A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic having K inputs (a “K-LUT”). The K-LUT is configured to input the binary input signals at respective inputs of the K-LUT logic cell and to provide, at a plurality of outputs of the K-LUT logic cell, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals. An input line network includes a network of input lines, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT. An output line network includes a network of output lines, the output lines configured to receive, from the K-LUT, output signals that represent the binary result signals and to provide the output signals to the PLD routing architecture. The described LUT's can perform arithmetic efficiently, as well as non-arithmetic functions.

    摘要翻译： 可编程逻辑器件（PLD）包括通过PLD路由架构连接的多个逻辑阵列块（LAB）。 至少一个LAB包括可配置为在多个级中算术组合多个二进制输入信号的逻辑元件（LE）。 LE包括具有K个输入（“K-LUT”）的查找表（LUT）逻辑。 K-LUT被配置为在K-LUT逻辑单元的相应输入处输入二进制输入信号，并且在K-LUT逻辑单元的多个输出处提供指示至少两个 二进制输入信号的算术组合的多级。 输入线网络包括输入线路网络，输入线路可配置为从PLD路由架构接收代表二进制输入信号的输入信号，并将输入信号提供给K-LUT。 输出线网络包括输出线网络，输出线路被配置为从K-LUT接收表示二进制结果信号的输出信号，并向PLD路由架构提供输出信号。 所描述的LUT可以有效地执行算术，以及非算术函数。