公开(公告)号：US20190333851A1

公开(公告)日：2019-10-31

申请号：US15965576

申请日：2018-04-27

Applicant: Rahul Agarwal ,  Milind S. Bhagavat ,  Priyal Shah

Inventor： Rahul Agarwal ,  Milind S. Bhagavat ,  Priyal Shah

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: Various fan-out devices are disclosed. In one aspect, a semiconductor chip device is provided that includes a redistribution layer (RDL) structure. The RDL structure includes plural metallization layers and plural polymer layers. One of the polymer layers is positioned over one of the metallization layers. The one of the metallization layers has conductor traces. The one of the polymer layers has an upper surface that is substantially planar at least where the conductor traces are positioned. A semiconductor chip is positioned on and electrically connected to the RDL structure. A molding layer is positioned on the RDL structure and at least partially encases the semiconductor chip.

公开(公告)号：US20190326221A1

公开(公告)日：2019-10-24

申请号：US15961222

申请日：2018-04-24

Applicant: Milind S. Bhagavat ,  Rahul Agarwal

Inventor： Milind S. Bhagavat ,  Rahul Agarwal

IPC: H01L23/538 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L25/18

Abstract: Various multi-die arrangements and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing a semiconductor chip device is provided. A redistribution layer (RDL) structure is fabricated with a first side and second side opposite to the first side. An interconnect chip is mounted on the first side of the RDL structure. A first semiconductor chip and a second semiconductor chip are mounted on the second side of the RDL structure after mounting the interconnect chip. The RDL structure and the interconnect chip electrically connect the first semiconductor chip to the second semiconductor chip.

公开(公告)号：US10312221B1

公开(公告)日：2019-06-04

申请号：US15844575

申请日：2017-12-17

Applicant: Rahul Agarwal ,  Kaushik Mysore Srinivasa Setty ,  Milind S. Bhagavat ,  Brett P. Wilkerson

Inventor： Rahul Agarwal ,  Kaushik Mysore Srinivasa Setty ,  Milind S. Bhagavat ,  Brett P. Wilkerson

IPC: H01L23/52 ,  H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/49811 ,  H01L23/5384 ,  H01L24/10

Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device includes a stack of plural semiconductor chips. Each two adjacent semiconductor chips of the plural semiconductor chips is electrically connected by plural interconnects and physically connected by a first insulating bonding layer. A first stack of dummy chips is positioned opposite a first side of the stack of semiconductor chips and separated from the plural semiconductor chips by a first gap. Each two adjacent of the first dummy chips are physically connected by a second insulating bonding layer. A second stack of dummy chips is positioned opposite a second side of the stack of semiconductor chips and separated from the plural semiconductor chips by a second gap. Each two adjacent of the second dummy chips are physically connected by a third insulating bonding layer. The first, second and third insulating bonding layers include a first insulating layer and a second insulating layer bonded to the first insulating layer. An insulating layer is in the first gap and another insulating layer is in the second gap.

公开(公告)号：US20190164936A1

公开(公告)日：2019-05-30

申请号：US15826054

申请日：2017-11-29

Applicant: Rahul Agarwal ,  Milind S. Bhagavat

Inventor： Rahul Agarwal ,  Milind S. Bhagavat

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538

Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a front side and a back side and plural through chip vias. The through chip vias have a first footprint. The back side is configured to have a second semiconductor chip stacked thereon. The second semiconductor chip includes plural interconnects that have a second footprint larger than the first footprint. The back side includes a backside interconnect structure configured to connect to the interconnects and provide fanned-in pathways to the through chip vias.

公开(公告)号：US09123698B2

公开(公告)日：2015-09-01

申请号：US13173456

申请日：2011-06-30

Applicant: Milind S. Bhagavat ,  Seyed Mahdi Saeidi ,  Tak Sang Yeung

Inventor： Milind S. Bhagavat ,  Seyed Mahdi Saeidi ,  Tak Sang Yeung

IPC: H01L23/34 ,  H01L23/467 ,  H05K7/20

CPC classification number: H01L23/467 ,  H01L23/3675 ,  H01L2924/0002 ,  H05K7/20136 ,  H05K7/20145 ,  H05K7/20154 ,  H01L2924/00

Abstract: Methods, systems, and apparatuses are described for cooling electronic devices. The electrical device includes an integrated circuit die (IC) having opposing first and second surfaces, a plurality of interconnects on the second surface of the IC die that enable the IC die to be coupled to a substrate, and a flexural plate wave device. The flexural plate wave device is configured to generate a stream of air to flow across the electrical device to cool the IC die during operation of the IC die.

Abstract translation: 描述了用于冷却电子设备的方法，系统和装置。 电气装置包括具有相对的第一和第二表面的集成电路管芯（IC），IC模头的第二表面上的使得IC管芯能够耦接到衬底的多个互连件，以及弯曲板形波装置。 弯曲板波装置被配置为产生流过电气装置的空气流，以在IC管芯的工作期间冷却IC管芯。

公开(公告)号：US08267745B2

公开(公告)日：2012-09-18

申请号：US12899262

申请日：2010-10-06

Applicant: Milind S. Bhagavat ,  Puneet Gupta ,  Roland R. Vandamme ,  Takuto Kazama ,  Noriyuki Tachi

Inventor： Milind S. Bhagavat ,  Puneet Gupta ,  Roland R. Vandamme ,  Takuto Kazama ,  Noriyuki Tachi

IPC: B24B1/00

CPC classification number: B24B7/228 ,  B24B7/17 ,  B24B37/08 ,  B24B37/28 ,  B24B41/061

Abstract: Methods for holding a workpiece with a hydrostatic pad are disclosed herein. The pad includes hydrostatic pockets formed in a face of the body directly opposed to the wafer. The pockets are adapted for receiving fluid through the body and into the pockets to provide a barrier between the body face and the workpiece while still applying pressure to hold the workpiece during grinding. The hydrostatic pads allow the wafer to rotate relative to the pads about their common axis. The pockets are oriented to reduce hydrostatic bending moments that are produced in the wafer when the grinding wheels shift or tilt relative to the hydrostatic pads, helping prevent nanotopology degradation of surfaces of the wafer commonly caused by shift and tilt of the grinding wheels.

Abstract translation: 本文公开了用静压垫保持工件的方法。 衬垫包括形成在与晶片直接相对的身体的表面中的静水压凹坑。 凹穴适于接收流体通过主体并进入凹穴，以在主体面和工件之间提供阻挡物，同时在研磨期间仍然施加压力以保持工件。 静压垫允许晶片相对于垫围绕它们的公共轴线旋转。 当砂轮相对于静液压垫移动或倾斜时，袋被定向成减小在晶片中产生的流体静力弯矩，有助于防止通常由砂轮的移动和倾斜引起的晶片表面的纳米拓扑降解。

公开(公告)号：US08066553B2

公开(公告)日：2011-11-29

申请号：US10598851

申请日：2005-01-20

Applicant: Milind S. Bhagavat ,  Puneet Gupta ,  Roland Vandamme ,  Takuto Kazama ,  Noriyuki Tachi

Inventor： Milind S. Bhagavat ,  Puneet Gupta ,  Roland Vandamme ,  Takuto Kazama ,  Noriyuki Tachi

IPC: B24B41/06

CPC classification number: B24B7/228 ,  B24B7/17 ,  B24B37/08 ,  B24B37/28 ,  B24B41/061

Abstract: A hydrostatic pad for use in holding a semiconductor wafer during grinding of the wafer by grinding wheels. The pad includes hydrostatic pockets formed in a face of the body directly opposed to the wafer. The pockets are adapted for receiving fluid through the body and into the pockets to provide a barrier between the body face and the workpiece while still applying pressure to hold the workpiece during grinding. The hydrostatic pads allow the wafer to rotate relative to the pads about their common axis. The pockets are oriented to reduce hydrostatic bending moments that are produced in the wafer when the grinding wheels shift or tilt relative to the hydrostatic pads, helping prevent nanotopology degradation of surfaces of the wafer commonly caused by shift and tilt of the grinding wheels.

Abstract translation: 一种静压垫，用于在通过研磨轮磨削晶片时保持半导体晶片。 衬垫包括形成在与晶片直接相对的身体的表面中的静水压凹坑。 凹穴适于接收流体通过主体并进入凹穴，以在主体面和工件之间提供阻挡物，同时在研磨期间仍然施加压力以保持工件。 静压垫允许晶片相对于垫围绕其公共轴线旋转。 当砂轮相对于静液压垫移动或倾斜时，袋被定向成减小在晶片中产生的流体静力弯矩，有助于防止通常由砂轮的移动和倾斜引起的晶片表面的纳米拓扑降解。

公开(公告)号：US20200035606A1

公开(公告)日：2020-01-30

申请号：US16048826

申请日：2018-07-30

Applicant: Milind S. Bhagavat ,  Lei Fu ,  Farshad Ghahghahi

Inventor： Milind S. Bhagavat ,  Lei Fu ,  Farshad Ghahghahi

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/16 ,  H01L23/31 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L21/683

Abstract: Various arrangements of multi-RDL structure devices are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer structure and a second redistribution layer structure mounted on the first redistribution layer structure. A first semiconductor chip is mounted on the second redistribution layer structure and electrically connected to both the second redistribution layer structure and the first redistribution layer structure.

公开(公告)号：US10529693B2

公开(公告)日：2020-01-07

申请号：US15826054

申请日：2017-11-29

Applicant: Rahul Agarwal ,  Milind S. Bhagavat

Inventor： Rahul Agarwal ,  Milind S. Bhagavat

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L23/522 ,  H01L23/498 ,  H01L21/48 ,  H01L23/48

Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a front side and a back side and plural through chip vias. The through chip vias have a first footprint. The back side is configured to have a second semiconductor chip stacked thereon. The second semiconductor chip includes plural interconnects that have a second footprint larger than the first footprint. The back side includes a backside interconnect structure configured to connect to the interconnects and provide fanned-in pathways to the through chip vias.

公开(公告)号：US20200006280A1

公开(公告)日：2020-01-02

申请号：US16023399

申请日：2018-06-29

Applicant: Priyal Shah ,  Milind S. Bhagavat

Inventor： Priyal Shah ,  Milind S. Bhagavat

IPC: H01L23/00

Abstract: Various chip stacks and methods and structures of interconnecting the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip that has a first glass layer and plural first groups of plural conductor pads in the first glass layer. Each of the plural first groups of conductor pads is configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a plurality interconnects that connect the first semiconductor chip to the second semiconductor chip. The first glass layer is configured to bond to a second glass layer of the second semiconductor chip.