公开(公告)号：US20250106072A1

公开(公告)日：2025-03-27

申请号：US18882046

申请日：2024-09-11

Applicant: NXP USA, INC.

Inventor： Guillaume Mouret ,  Fabien Viemon ,  Guerric Panis ,  Nicolas Astruc

IPC: H04L25/02 ,  H03F3/19 ,  H04B3/20

Abstract: The disclosure relates to a transceiver physical layer interface. Example embodiments include a transmission line transceiver (401) comprising: first and second terminals (406a, 406b); a control module (416); an amplifier module (414) connected between the control module (416) and the first and second terminals (406a, 406b); a switchable termination resistance circuit (408, 410) connected between the first and second terminals (406a, 406b), the switchable termination resistance circuit (408, 410) comprising a termination resistance (408) connected in series with a switch (410) controllable by the control module (416); a pair of series connected resistors (418a, 418b) connected between the first and second terminals (406a, 406b); a capacitor (420) connected between a node (423) connecting the pair of series connected resistors (418a, 418b) and a common node (422), wherein the control module (416) is configured to open the switch (410) to disconnect the termination resistance (408) during transmission of a signal via a transmission line (403) capacitively connected to the first and second terminals (406a, 406b).

公开(公告)号：US20250095339A1

公开(公告)日：2025-03-20

申请号：US18813813

申请日：2024-08-23

Applicant: NXP USA, Inc.

Inventor： Michael Andreas Staudenmaier ,  Iani Bogdan Almajan ,  Stephan Matthias Herrmann ,  Vincent Aubineau

IPC: G06V10/774 ,  G06T7/00 ,  G06V10/26 ,  G06V10/94 ,  G06V20/90

Abstract: A system, method, and apparatus are provided for verifying functional safety of an image signal processor (ISP) by configuring one or more edge pattern settings in a test pattern generator; activating the test pattern generator to generate test pattern data by modulating a sequence of pseudo random number values with a sequence of values from an edge pattern; processing the test pattern data at the ISP to generate ISP test output data; generating a checksum value of the ISP test output data; and comparing the checksum value with a reference checksum value to verify a functionality of the ISP.

公开(公告)号：US20250093934A1

公开(公告)日：2025-03-20

申请号：US18467213

申请日：2023-09-14

Applicant: NXP USA, Inc.

Inventor： Siamak Delshadpour ,  Xu Zhang

IPC: G06F1/30 ,  G06F1/22 ,  G06F13/40 ,  H03K17/28 ,  H03K17/30 ,  H04L25/02

Abstract: One example discloses a driver circuit, comprising: a first transistor (QTN) coupled to a first differential input (IN) and a power supply input (VCC); a second transistor (QTP) coupled to a second differential input (IP) and the power supply input; a third transistor (QBN) coupled to a first differential output (ON); a fourth transistor (QBP) coupled to a second differential output (OP); a first resistance (RP1) coupling the first transistor (QTN) to the third transistor (QBN); a second resistance (RP2) coupling the second transistor (QTP) to the fourth transistor (QBP); and a controller coupled to the power supply input; wherein the controller is configured to detect a ramp-down of a power supply coupled to the power supply input and in response disable a set of circuit elements in the driver circuit.

公开(公告)号：US20250088115A1

公开(公告)日：2025-03-13

申请号：US18827067

申请日：2024-09-06

Applicant: NXP USA, Inc.

Inventor： Peter Theodorus Johannes Degen ,  Wilhelmus Hinderikus Maria Langeslag

IPC: H02M3/335 ,  H02M1/32

Abstract: A controller for a switched mode power supply comprising a primary winding configured to receive an input voltage at a first terminal of the primary winding. A first capacitor is coupled in series between a second terminal of the primary winding and a reference terminal configured to be coupled to a reference voltage. A secondary winding is configured to provide an output voltage of the SMPS based on the input voltage and an auxiliary winding is inductively coupled to one or both of the primary winding and the secondary winding and is configured to provide an auxiliary voltage based at least on a voltage of the first capacitor. The controller is configured to output an overvoltage signal indicative of an overvoltage across the first capacitor, based on a comparison of the auxiliary voltage during a primary stroke of the SMPS to a threshold indicative of a predetermined maximum first capacitor voltage.

公开(公告)号：US20250087554A1

公开(公告)日：2025-03-13

申请号：US18499660

申请日：2023-11-01

Applicant: NXP USA, Inc.

Inventor： Chetan Sharma ,  Dinesh Upreti

IPC: H01L23/38 ,  H01L23/34 ,  H01L23/467

Abstract: Apparatus and method for improving reliability of an integrated circuit. The apparatus comprises an integrated circuit and a heatsink which is in contact with package of the integrated circuit. A Peltier element comprises a first surface and a second surface and is positioned in a cavity of the heatsink. Based on a first indication from a sensor, a controller applies a first polarity to a first terminal and second terminal of the Peltier element to reduce a temperature of the second surface to cool the integrated circuit and based on a second indication from the sensor, the controller applies a second polarity to the first terminal and second terminal of the Peltier element to increase the temperature of the second surface to heat the integrated circuit.

公开(公告)号：US12250043B2

公开(公告)日：2025-03-11

申请号：US18328280

申请日：2023-06-02

Applicant: NXP USA, Inc.

Inventor： Young Hoon Kwon ,  Liwen Chu ,  Sudhir Srinivasa ,  Hongyuan Zhang ,  Huiling Lou

IPC: H04B7/06 ,  H04B7/0413 ,  H04W72/04 ,  H04W88/02 ,  H04W88/06

Abstract: Various embodiments relate to a system and method for joint sounding by a client with a master access point (AP) and a slave (AP), including: receiving a message from the master AP; applying network allocation vector (NAV) rules to update a NAV values, wherein the received message is treated as an intra-basic service set (BSS) message when the transmit address (TA) of the received message has a prespecified value; receiving a first trigger frame; and transmitting a first channel state information (CSI) to the master AP when the channel is idle based upon the updated NAV value in response to the trigger frame.

公开(公告)号：US12249826B2

公开(公告)日：2025-03-11

申请号：US17937648

申请日：2022-10-03

Applicant: NXP USA, Inc.

Inventor： Andrea Milanesi

IPC: H02H9/02 ,  H02H1/00 ,  H02M3/155

Abstract: One example discloses a current limited power device, including: a switch; an output coupled to the switch; a sensor coupled to sense a voltage across a parasitic diode within the switch; and an output current limiter circuit coupled to reduce a output current (Iout) from the output of the power device if the voltage across the parasitic diode exceeds a threshold level.

公开(公告)号：US12231042B2

公开(公告)日：2025-02-18

申请号：US17734993

申请日：2022-05-02

Applicant: NXP USA, Inc.

Inventor： John Pigott ,  Trevor Mark Newlin

IPC: H02M3/158

Abstract: Embodiments of a power stage for a direct current (DC)-DC converter and a DC-DC converter are disclosed. In an embodiment, a power stage for a DC-DC converter includes an input terminal from which input power of the DC-DC converter with an input DC voltage is received, a high-side segment connected between the input DC voltage and an output signal of the power stage, and a low-side segment connected between the output signal of the power stage and ground. At least one of the high-side segment and the low-side segment includes stacked transistors having isolation terminals that are biased to reduce substrate injection.

公开(公告)号：US20250055171A1

公开(公告)日：2025-02-13

申请号：US18366965

申请日：2023-08-08

Applicant: NXP USA, Inc.

Inventor： Joseph Staudinger ,  Michael Lee Fraser

IPC: H01P5/16 ,  H03F3/20

Abstract: A quadrature coupler includes four ports, four inductors, and six capacitors. The first through third capacitors are coupled in series between the first and fourth ports. A first intermediate node is between the first and second capacitors. A second intermediate node is between the second and third capacitors. The fourth through sixth capacitors are coupled in series between the second and third ports. A third intermediate node is between the fourth and fifth capacitors, and a fourth intermediate node is between the fifth and sixth capacitors. The first inductor is coupled between the first and second ports. The second inductor is coupled between the first and third intermediate nodes. The third inductor is coupled between the second and fourth intermediate nodes. The fourth inductor is coupled between the fourth and third ports. Variable tuning networks may be coupled between the first and fourth ports and the second and third ports.

公开(公告)号：US12224692B2

公开(公告)日：2025-02-11

申请号：US18059337

申请日：2022-11-28

Applicant: NXP USA, Inc.

Inventor： Matej Pacha

IPC: H02P6/182 ,  H02P29/028

Abstract: An electric motor controller having fault detection comprises: a driver circuit configured to drive an electric motor in response to a received speed demand signal; a measurement circuit configured to measure current through windings of the electric motor, the measurement circuit comprising a back emf, BEMF, observer configured to determine an estimated BEMF value, a BEMF error threshold and an estimated rotor angular speed value from the measured currents; a detector circuit configured to receive the rotor speed demand signal, the estimated BEMF value, the BEMF error threshold, the estimated rotor angular speed value and a measured rotor speed from a rotor speed sensor on the electric motor and to detect a fault in the electric motor controller if the estimated BEMF value lies outside the BEMF error threshold and the measured rotor speed is within a defined rotor speed error threshold.