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公开(公告)号：US20250080123A1
公开(公告)日：2025-03-06
申请号：US18459289
申请日：2023-08-31
Applicant: NXP USA, Inc.
Inventor： Pragya Priya Malakar , John Pigott
Abstract: Oscillator circuitry and methods of operation thereof are provided in which the oscillator circuitry includes at least a first oscillator, a second oscillator, and a lock detector. The first oscillator is configured to generate a first clock signal. The second oscillator is configured to generate a second clock signal. The lock detector is configured to detect a stable phase lock between the first clock signal and the second clock signal and to switch an output of the oscillator circuitry from the first clock signal to the second clock signal in response to detecting the stable phase lock.
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公开(公告)号：US20230318454A1
公开(公告)日：2023-10-05
申请号：US18193454
申请日：2023-03-30
Applicant: NXP USA, Inc.
Inventor： Nameer Ahmed Khan , Olivier Trescases , John Pigott , Hendrik Johannes Bergveld , Gerard Villar Piqué , Alaa Eldin Y El Sherif
Abstract: Disclosed are a controller and power converter having a main buck converter connected between a first input voltage and ground and having a main output, a bidirectional auxiliary converter connected between a second terminal and ground and having an auxiliary output connected to the main output, an output capacitor, and an auxiliary capacitor connected between the second terminal and the ground for providing a second terminal voltage at the second terminal; the controller comprising: first control circuit configured to operate the main converter at a first frequency; and second control circuit configured to operate the auxiliary converter at a higher frequency; the first control circuit being further configured to operate the main converter in dependence on the second terminal voltage; and the second control circuit being further configured to operate the auxiliary converter to control the voltage at the main output terminal.
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公开(公告)号：US10116287B2
公开(公告)日：2018-10-30
申请号：US15409024
申请日：2017-01-18
Applicant: NXP USA, Inc.
Inventor： Tristan Bosvieux , Jeremy Guillermand , John Pigott
Abstract: A switched current control module comprises a hysteretic control component arranged to receive high and low threshold values and an indication of a current flow through a load, and to output a switched current control signal based on a comparison of the current flow indication to the high and low threshold values. A threshold generator is arranged to generate the high and low threshold values based on a base threshold value and a hysteretic excursion value. A base threshold value generator is arranged to generate the base threshold value based on the current flow indication and a setpoint value. A hysteretic excursion value generator is arranged to receive an indication of a switching frequency of the switched current control signal output by the hysteretic control component, and to generate the hysteretic excursion value based on the indicated switching frequency of the switched current control signal.
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公开(公告)号：US11619961B1
公开(公告)日：2023-04-04
申请号：US17645871
申请日：2021-12-23
Applicant: NXP USA, Inc.
Inventor： Stefano Pietri , John Pigott
Abstract: A bandgap reference correction circuit comprising a bandgap reference circuit comprising a first resistor; a first oscillator comprising a second resistor, wherein a frequency of a first oscillator output signal of the first oscillator depends on a resistance of the second resistor; and a compensation module configured to: receive the first oscillator output signal from the first oscillator and a reference frequency signal from a reference oscillator; determine the frequency of the first oscillator output signal using the reference frequency signal; and set a resistance of the first resistor based on the frequency of the first oscillator output signal.
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5.发明授权公开(公告)号：US10812080B2
公开(公告)日：2020-10-20
申请号：US16189424
申请日：2018-11-13
Applicant: NXP USA, Inc.
Inventor： John Pigott , Trevor Mark Newlin
IPC: H03K3/012 , H03K19/0175 , H03K19/0185
Abstract: A method for high-speed voltage level translation includes biasing a high-voltage (HV) gate of an HV transistor to an intermediate voltage with a bias device. A low-voltage (LV) transistor is activated with a positive voltage transition applied to an LV gate of the LV transistor, wherein the HV transistor is connected in series between an output and an LV drain of the LV transistor. The intermediate voltage is bootstrapped to a bootstrapped voltage in response to the positive voltage transition on the LV gate coupled to the HV gate through a capacitor therebetween. The output is discharged. A time constant, defined by a resistance of the bias device and a capacitance of the capacitor, is greater than a minimum time constant, thereby maintaining the bootstrapped voltage on the HV gate at or above a drive voltage for a minimum period to discharge the output to a minimum voltage.
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Patent Agency Ranking
公开(公告)号：US20250096799A1
公开(公告)日：2025-03-20
申请号：US18819313
申请日：2024-08-29
Applicant: NXP USA, INC.
Inventor： John Pigott , Vishnu Khemka , Tanuj Saxena
IPC: H03K17/687 , H01L27/06 , H03K17/74
Abstract: The present invention relates to a circuit comprising a self-conducting transistor referred to as power transistor, a further transistor referred to as control transistor, a further transistor referred to as first protection transistor, and a string referred to as a Zener string, which comprises at least one Zener diode, wherein the power transistor is coupled between a first terminal of the circuit and a first node of the circuit, wherein the control transistor is coupled between the first node and a second terminal of the circuit, wherein a gate terminal of the control transistor is coupled to a third terminal of the circuit, wherein the first protection transistor is coupled between the first node and the second terminal, and wherein the Zener string is coupled between the first terminal and a gate terminal of the first protection transistor.
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公开(公告)号：US12170254B2
公开(公告)日：2024-12-17
申请号：US17935032
申请日：2022-09-23
Applicant: NXP USA, Inc.
Inventor： Tanuj Saxena , John Pigott , Vishnu Khemka , Ljubo Radic , Ganming Qin
IPC: H01L23/62 , H03K17/082
Abstract: A semiconductor device has first and second current terminals and a control terminal that can be biased to form an electrically conductive path from the first current terminal to the second current terminal through a channel region is provided with a temperature-sensitive current limiting device. The current-limiting device is integrally formed from semiconductor material of the control terminal and is configured to cause a reduction in electrical current flowing through the channel region when the temperature of the device in the channel region exceeds a predetermined threshold temperature.
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公开(公告)号：US20240113045A1
公开(公告)日：2024-04-04
申请号：US17935032
申请日：2022-09-23
Applicant: NXP USA, Inc.
Inventor： Tanuj Saxena , John Pigott , Vishnu Khemka , Ljubo Radic , Ganming Qin
IPC: H01L23/62 , H03K17/082
CPC classification number: H01L23/62 , H03K17/0822 , H03K2217/0027
Abstract: A semiconductor device has first and second current terminals and a control terminal that can be biased to form an electrically conductive path from the first current terminal to the second current terminal through a channel region is provided with a temperature-sensitive current limiting device. The current-limiting device is integrally formed from semiconductor material of the control terminal and is configured to cause a reduction in electrical current flowing through the channel region when the temperature of the device in the channel region exceeds a predetermined threshold temperature.
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公开(公告)号：US10712763B2
公开(公告)日：2020-07-14
申请号：US16701393
申请日：2019-12-03
Applicant: NXP USA, INC.
Inventor： Guillaume Mouret , Thierry Michel Alain Sicard , John Pigott
Abstract: The present application relates to a sub-bandgap reference source circuit, which comprises a current mirror source, a first branch comprising a first BJT and a second branch comprising a second BJT, the first BJT having an emitter current density lower than an emitter current density of the second BJT, the first branch and the second branch being connected at a first node coupled to ground; a first voltage divider comprising first and second resistances coupled in series, the first resistance being coupled between a base terminal of the first BJT and a second node, the second resistor being coupled to ground; a second voltage divider comprising first and second resistances coupled in series, the first resistance being coupled between the second node and a base terminal of the second BJT, the second resistance being coupled to the first node; and an output terminal coupled to the second node.
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10.发明申请公开(公告)号：US20200153420A1
公开(公告)日：2020-05-14
申请号：US16189424
申请日：2018-11-13
Applicant: NXP USA, Inc.
Inventor： John Pigott , Trevor Mark Newlin
Abstract: A method for high-speed voltage level translation includes biasing a high-voltage (HV) gate of an HV transistor to an intermediate voltage with a bias device. A low-voltage (LV) transistor is activated with a positive voltage transition applied to an LV gate of the LV transistor, wherein the HV transistor is connected in series between an output and an LV drain of the LV transistor. The intermediate voltage is bootstrapped to a bootstrapped voltage in response to the positive voltage transition on the LV gate coupled to the HV gate through a capacitor therebetween. The output is discharged. A time constant, defined by a resistance of the bias device and a capacitance of the capacitor, is greater than a minimum time constant, thereby maintaining the bootstrapped voltage on the HV gate at or above a drive voltage for a minimum period to discharge the output to a minimum voltage.
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