公开(公告)号：US4922135A

公开(公告)日：1990-05-01

申请号：US271124

申请日：1988-11-14

Applicant: Pierre Mollier ,  Pascal Tannhof

Inventor： Pierre Mollier ,  Pascal Tannhof

IPC: H01L27/095 ,  H03K5/02 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/094 ,  H03K19/0952

CPC classification number: H03K19/09436 ,  H03K19/01721

Abstract: The present invention relates to a family of new GaAs MESFET logic circuits including push pull output buffers, which exhibits very strong output driving capability and very low power consumption at fast switching speeds. A 3 way OR/NOR circuit of this invention includes a standard differential amplifier, the first branch of which is controlled by logic input signals. The second branch includes a current switch controlled by a reference voltage. The differential amplifier provides first and second output signals simultaneously and complementary each other. The circuit further includes two push pull output buffers. The first output buffer comprises an active pull up device connected in series with an active pull down device, and the first circuit output signal is available at their common node or at the output terminal. The active pull up device is controlled by a first output signal of the differential amplifier, and the active pull down device is preferably controlled by the second output signal through an intermediate source follower buffer. The second output buffer is of similar structure. The depicted circuit is of the dual phase type. However, if only one phase of the circuit output signal is needed, the output buffer and the intermediate buffer can be eliminated. The number of devices can be even further reduced by eliminating the other remaining intermediate buffer.

公开(公告)号：US07254565B2

公开(公告)日：2007-08-07

申请号：US10137969

申请日：2002-05-03

Applicant: Ghislain Imbert De Tremiolles ,  Pascal Tannhof

Inventor： Ghislain Imbert De Tremiolles ,  Pascal Tannhof

IPC: G06E1/00 ,  G06E3/00 ,  G06F15/18 ,  G06G7/00 ,  G06N3/00 ,  G06N3/08 ,  G06N3/04

CPC classification number: G06K9/6276 ,  G06N3/063

Abstract: An improved Artificial Neural Network (ANN) is disclosed that comprises a conventional ANN, a database block, and a compare and update circuit. The conventional ANN is formed by a plurality of neurons, each neuron having a prototype memory dedicated to store a prototype and a distance evaluator to evaluate the distance between the input pattern presented to the ANN and the prototype stored therein. The database block has: all the prototypes arranged in slices, each slice being capable to store up to a maximum number of prototypes; the input patterns or queries to be presented to the ANN; and the distances resulting of the evaluation performed during the recognition/classification phase. The compare and update circuit compares the distance with the distance previously found for the same input pattern updates or not the distance previously stored.

Abstract translation: 公开了一种改进的人造神经网络（ANN），其包括常规ANN，数据库块以及比较和更新电路。 常规ANN由多个神经元形成，每个神经元具有专用于存储原型的原型存储器和距离评估器，以评估呈现给ANN的输入模式与存储在其中的原型之间的距离。 数据库块具有：所有原型以切片排列，每个切片能够存储最多数量的原型; 要呈现给ANN的输入模式或查询; 以及在识别/分类阶段期间进行评估的距离。 比较和更新电路将距离与先前发现的相同输入模式更新的距离进行比较，或将之前存储的距离进行比较。

公开(公告)号：US20070150621A1

公开(公告)日：2007-06-28

申请号：US11682547

申请日：2007-03-06

Applicant: Kerry Kravec ,  Ali Saidi ,  Jan Slyfield ,  Pascal Tannhof

Inventor： Kerry Kravec ,  Ali Saidi ,  Jan Slyfield ,  Pascal Tannhof

IPC: G06F3/00

CPC classification number: G06K9/6202 ,  G06K9/00986

Abstract: A parallel pattern detection engine (PPDE) comprise multiple processing units (PUs) customized to do various modes of pattern recognition. The PUs are loaded with different patterns and the input data to be matched is provided to the PUs in parallel. Each pattern has an Opcode that defines what action to take when a particular data in the input data stream either matches or does not match the corresponding data being compared during a clock cycle. Each of the PUs communicate selected information so that PUs may be cascaded to enable longer patterns to be matched or to allow more patterns to be processed in parallel for a particular input data stream.

公开(公告)号：US20050154916A1

公开(公告)日：2005-07-14

申请号：US10756904

申请日：2004-01-14

Applicant: Marc Boulanger ,  Clark Jeffries ,  C. Kinard ,  Kerry Kravec ,  Ravinder Sabhikhi ,  Ali Saidi ,  Jan Slyfield ,  Pascal Tannhof

Inventor： Marc Boulanger ,  Clark Jeffries ,  C. Kinard ,  Kerry Kravec ,  Ravinder Sabhikhi ,  Ali Saidi ,  Jan Slyfield ,  Pascal Tannhof

IPC: H04L9/00 ,  H04L12/24 ,  H04L29/06

CPC classification number: H04L63/1416 ,  H04L63/1441

Abstract: An intrusion detection system (IDS) comprises a network processor (NP) coupled to a memory unit for storing programs and data. The NP is also coupled to one or more parallel pattern detection engines (PPDE) which provide high speed parallel detection of patterns in an input data stream. Each PPDE comprises many processing units (PUs) each designed to store intrusion signatures as a sequence of data with selected operation codes. The PUs have configuration registers for selecting modes of pattern recognition. Each PU compares a byte at each clock cycle. If a sequence of bytes from the input pattern match a stored pattern, the identification of the PU detecting the pattern is outputted with any applicable comparison data. By storing intrusion signatures in many parallel PUs, the IDS can process network data at the NP processing speed. PUs may be cascaded to increase intrusion coverage or to detect long intrusion signatures.

Abstract translation: 入侵检测系统（IDS）包括耦合到用于存储程序和数据的存储器单元的网络处理器（NP）。 NP还耦合到一个或多个并行模式检测引擎（PPDE），其提供对输入数据流中的模式的高速并行检测。 每个PPDE包括许多处理单元（PU），每个处理单元被设计为将入侵签名存储为具有所选操作码的数据序列。 PU具有用于选择模式识别模式的配置寄存器。 每个PU在每个时钟周期比较一个字节。 如果来自输入模式的字节序列与存储的模式匹配，则用任何适用的比较数据输出检测模式的PU的识别。 通过在多个并行PU中存储入侵签名，IDS可以以NP处理速度处理网络数据。 PU可以级联以增加入侵覆盖或检测长入侵签名。

公开(公告)号：US06347309B1

公开(公告)日：2002-02-12

申请号：US09223478

申请日：1998-12-30

Applicant: Ghislain Imbert De Tremiolles ,  Pascal Tannhof

Inventor： Ghislain Imbert De Tremiolles ,  Pascal Tannhof

IPC: G06N306

CPC classification number: G06K9/6271 ,  G06N3/063

Abstract: The improved neural network of the present invention results from the combination of a dedicated logic block with a conventional neural network based upon a mapping of the input space usually employed to classify an input data by computing the distance between said input data and prototypes memorized therein. The improved neural network is able to classify an input data, for instance, represented by a vector A even when some of its components are noisy or unknown during either the learning or the recognition phase. To that end, influence fields of various and different shapes are created for each neuron of the conventional neural network. The logic block transforms at least some of the n components (A1, . . . , An) of the input vector A into the m components (V1, . . . , Vm) of a network input vector V according to a linear or non-linear transform function F. In turn, vector V is applied as the input data to said conventional neural network. The transform function F is such that certain components of vector V are not modified, e.g. Vk=Aj, while other components are transformed as mentioned above, e.g. Vi=Fi(A1, . . . , An). In addition, one (or more) component of vector V can be used to compensate an offset that is present in the distance evaluation of vector V. Because, the logic block is placed in front of the said conventional neural network any modification thereof is avoided.

Abstract translation: 本发明的改进的神经网络是基于通常用于通过计算所述输入数据与其中存储的原型之间的距离来对输入数据进行分类的输入空间的映射，将专用逻辑块与传统神经网络的组合。 改进的神经网络能够对例如由向量A表示的输入数据进行分类，即使在学习或识别阶段期间，其一些组件是噪声或未知的。 为此，为传统神经网络的每个神经元创建各种不同形状的影响场。 逻辑块根据线性或非线性将输入矢量A的n个分量（A1，...，An）中的至少一些变换成网络输入矢量V的m个分量（V1，...，Vm） 然后将矢量V作为输入数据施加到所述常规神经网络。 变换函数F使得向量V的某些分量不被修改，例如， Vk = Aj，而其它组分如上所述被转化，例如。 Vi = Fi（A1，...，An）。 另外，矢量V的一个（或多个）分量可以用于补偿矢量V的距离评估中存在的偏移。因为逻辑块被放置在所述传统神经网络的前面，所以避免了其任何修改 。

公开(公告)号：US20070150623A1

公开(公告)日：2007-06-28

申请号：US11682623

申请日：2007-03-06

Applicant: Kerry Kravec ,  Ali Saidi ,  Jan Styfield ,  Pascal Tannhof

Inventor： Kerry Kravec ,  Ali Saidi ,  Jan Styfield ,  Pascal Tannhof

IPC: G06F3/00

CPC classification number: G06K9/6202 ,  G06K9/00986

Abstract: A parallel pattern detection engine (PPDE) comprise multiple processing units (PUs) customized to do various modes of pattern recognition. The PUs are loaded with different patterns and the input data to be matched is provided to the PUs in parallel. Each pattern has an Opcode that defines what action to take when a particular data in the input data stream either matches or does not match the corresponding data being compared during a clock cycle. Each of the PUs communicate selected information so that PUs may be cascaded to enable longer patterns to be matched or to allow more patterns to be processed in parallel for a particular input data stream.

公开(公告)号：US07133854B2

公开(公告)日：2006-11-07

申请号：US10014166

申请日：2001-12-11

Applicant: Ghislain Imbert De Tremiolles ,  Pascal Tannhof

Inventor： Ghislain Imbert De Tremiolles ,  Pascal Tannhof

IPC: G10L19/12 ,  G06E1/00 ,  G06E3/00 ,  G06F15/18 ,  G06G7/00 ,  G06F15/16

CPC classification number: G06T9/00

Abstract: Let us consider a plurality of input patterns having an essential characteristic in common but which differ on at least one parameter (this parameter modifies the input pattern in some extent but not this essential characteristic for a specific application). During the learning phase, each input pattern is normalized in a normalizer, before it is presented to a classifier. If not recognized, it is learned, i.e. the normalized pattern is stored in the classifier as a prototype with its category associated thereto. From a predetermined reference value of that parameter, the normalizer computes an element related to said parameter which allows to set the normalized pattern from the input pattern and vice versa to retrieve the input pattern from the normalized pattern. As a result, all these input patterns are represented by the same normalized pattern. The above method and circuits allow to reduce the number of required prototypes in the classifier, improving thereby its response quality.

公开(公告)号：US06983265B2

公开(公告)日：2006-01-03

申请号：US10316250

申请日：2002-12-10

Applicant: Pascal Tannhof ,  Ghislain Imbert de Tremiolles

Inventor： Pascal Tannhof ,  Ghislain Imbert de Tremiolles

IPC: G06N3/06

CPC classification number: G06K9/6276 ,  G06N3/04

Abstract: A method is described to improve the data transfer rate between a personal computer or a host computer and a neural network implemented in hardware by merging a plurality of input patterns into a single input pattern configured to globally represent the set of input patterns. A base consolidated vector (U′*n) representing the input pattern is defined to describe all the vectors (Un, . . . , Un+6) representing the input patterns derived thereof (U′n, . . . , U′n+6) by combining components having fixed and ‘don't care’ values. The base consolidated vector is provided only once with all the components of the vectors. An artificial neural network (ANN) is then configured as a combination of sub-networks operating in parallel. In order to compute the distances with an adequate number of components, the prototypes are to include also components having a definite value and ‘don't care’ conditions. During the learning phase, the consolidated vectors are stored as prototypes. During the recognition phase, when a new base consolidated vector is provided to ANN, each sub-network analyses a portion thereof After computing all the distances, they are sorted one sub-network at a time to obtain the distances associated to each vector.

Abstract translation: 描述了一种方法，以通过将多个输入模式合并为被配置为全局地表示该组输入模式的单个输入模式来改善个人计算机或主机计算机与硬件中实现的神经网络之间的数据传输速率。 定义表示输入模式的基本合并向量（U'* N n N）来描述所有向量（U N，N，N，N，N） 代表其导出的输入模式（U'，N“，...，U”n + 6）的组合，通过组合具有固定的“不” 护理价值观。 基本合并向量仅与向量的所有分量一起提供。 然后将人造神经网络（ANN）配置为并行操作的子网络的组合。 为了用足够数量的组件计算距离，原型还包括具有确定值和“无关紧要”条件的组件。 在学习阶段，合并的向量存储为原型。 在识别阶段，当向ANN提供新的基本合并向量时，每个子网络分析其一部分。在计算所有距离之后，它们一次对一个子网进行排序，以获得与每个向量相关联的距离。

公开(公告)号：US5740326A

公开(公告)日：1998-04-14

申请号：US486658

申请日：1995-06-07

Applicant: Jean-Yves Boulet ,  Pascal Tannhof ,  Guy Paillet

Inventor： Jean-Yves Boulet ,  Pascal Tannhof ,  Guy Paillet

IPC: G06F15/18 ,  G06F7/544 ,  G06N3/00 ,  G06N3/04 ,  G06N3/06 ,  G06N3/063

CPC classification number: G06K9/6271 ,  G06F7/544 ,  G06N3/063 ,  G06K2209/01

Abstract: In a neural network of N neuron circuits, having an engaged neuron's calculated p bit wide distance between an input vector and a prototype vector and stored in the weight memory thereof, an aggregate search/sort circuit (517) of N engaged neurons' search/sort circuits. The aggregate search/sort circuit determines the minimum distance among the calculated distances. Each search/sort circuit (502-1) has p elementary search/sort units connected in series to form a column, such that the aggregate circuit is a matrix of elementary search/sort units. The distance bit signals of the same bit rank are applied to search/sort units in each row. A feedback signal is generated by ORing in an OR gate (12.1) all local search/sort output signals from the elementary search/sort units of the same row. The search process is based on identifying zeroes in the distance bit signals, from the MSB's to the LSB's. As a zero is found in a row, all the columns with a one in that row are excluded from the subsequent row search. The search process continues until only one distance, the minimum distance, remains and is available at the output of the OR circuit. The above described search/sort circuit may further include a latch allowing the aggregate circuit to sort remaining distances in increasing order.

Abstract translation: 在N个神经元电路的神经网络中，在输入向量和原型向量之间具有被约束的神经元计算的p位宽的距离并存储在其权重存储器中，N个接收的神经元的搜索/ 排序电路。 聚合搜索/分类电路确定计算出的距离之间的最小距离。 每个搜索/分类电路（502-1）具有串联连接的p个基本搜索/分类单元以形成列，使得聚合电路是基本搜索/分类单元的矩阵。 相同位等级的距离位信号被应用于每行的搜索/排序单元。 通过在或门（12.1）中对来自同一行的基本搜索/排序单元的所有本地搜索/排序输出信号进行“或”生成反馈信号。 搜索过程基于识别距离位信号中的零，从MSB到LSB。 由于在一行中找到零，所以在该行中具有一个列的列将从后续行搜索中排除。 搜索过程继续，直到只有一个距离，最小距离保持，并且在OR电路的输出端可用。 上述搜索/分类电路还可以包括允许聚合电路以增加的顺序对剩余距离进行排序的锁存器。

公开(公告)号：US5621863A

公开(公告)日：1997-04-15

申请号：US481591

申请日：1995-06-07

Applicant: Jean-Yves Boulet ,  Didier Louis ,  Catherine Godefroy ,  Andre Steimle ,  Pascal Tannhof ,  Guy Paillet

Inventor： Jean-Yves Boulet ,  Didier Louis ,  Catherine Godefroy ,  Andre Steimle ,  Pascal Tannhof ,  Guy Paillet

IPC: G06F15/18 ,  G06K9/66 ,  G06N3/00 ,  G06N3/06 ,  G06N3/063 ,  G06N3/08

CPC classification number: G06K9/6272 ,  G06K9/00986 ,  G06N3/063

Abstract: In a neural network comprised of a plurality of neuron circuits, an improved neuron circuit that generates local result signals, e.g. of the fire type, and a local output signal of the distance or category type. The neuron circuit which is connected to buses that transport input data (e.g. the input category) and control signals. A multi-norm distance evaluation circuit calculates the distance D between the input vector and a prototype vector stored in a R/W memory circuit. A distance compare circuit compares this distance D with either the stored prototype vector's actual influence field or the lower limit thereof to generate first and second comparison signals. An identification circuit processes the comparison signals, the input category signal, the local category signal and a feedback signal to generate local result signals that represent the neuron circuit's response to the input vector. A minimum distance determination circuit determines the minimum distance Dmin among all the calculated distances from all of the neuron circuits of the neural network and generates a local output signal of the distance type. The circuit may be used to search and sort categories. The feed-back signal is collectively generated by all the neuron circuits by ORing all the local distances/categories. A daisy chain circuit is serially connected to corresponding daisy chain circuits of two adjacent neuron circuits to chain the neurons together. The daisy chain circuit also determines the neuron circuit state as free or engaged. Finally, a context circuitry enables or inhibits neuron participation with other neuron circuits in generation of the feedback signal.

Abstract translation: 在由多个神经元电路组成的神经网络中，生成本地结果信号的改进的神经元电路，例如， 的火灾类型，以及距离或类别类型的本地输出信号。 连接到传送输入数据（例如输入类别）和控制信号的总线的神经元电路。 多范围距离评估电路计算输入矢量和存储在R / W存储器电路中的原型矢量之间的距离D. 距离比较电路将该距离D与存储的原型矢量的实际影响场或其下限进行比较，以产生第一和第二比较信号。 识别电路处理比较信号，输入类别信号，局部类别信号和反馈信号，以产生表示神经元电路对输入矢量的响应的本地结果信号。 最小距离确定电路确定来自神经网络的所有神经元电路的所有计算距离中的最小距离Dmin，并产生距离类型的局部输出信号。 该电路可用于搜索和分类。 所有的神经元电路通过对所有的局部距离/类别进行OR运算来共同地产生反馈信号。 菊花链电路串联连接到两个相邻神经元电路的相应菊花链电路，以将神经元链接在一起。 菊花链电路还将神经元电路状态确定为自由或接合。 最后，上下文电路在反馈信号的产生中实现或抑制与其他神经元电路的神经元参与。