公开(公告)号：US20100164606A1

公开(公告)日：2010-07-01

申请号：US12463390

申请日：2009-05-09

Applicant: Prakash EASWARAN ,  Prasenjit BHOWMIK ,  Sumeet MATHUR

Inventor： Prakash EASWARAN ,  Prasenjit BHOWMIK ,  Sumeet MATHUR

IPC: G05F1/10

CPC classification number: G05F3/26 ,  H03F1/301

Abstract: A method for biasing a MOS transistor includes AC coupling an input signal from an amplifier stage to a gate of the MOS transistor. The method includes connecting a pair of diodes in an opposing parallel configuration to a bias transistor and a current source. Further, the method includes generating a DC bias voltage through the bias transistor and the current source. The method also includes clamping the voltage at drain of the bias transistor to a fixed voltage by a clamping circuit. Further, the method includes coupling the DC bias voltage to the gate of the MOS transistor through the pair of diodes.

Abstract translation: 用于偏置MOS晶体管的方法包括将来自放大器级的输入信号AC耦合到MOS晶体管的栅极。 该方法包括将一对相反并联配置的二极管连接到偏置晶体管和电流源。 此外，该方法包括通过偏置晶体管和电流源产生DC偏置电压。 该方法还包括通过钳位电路将偏置晶体管的漏极处的电压钳位到固定电压。 此外，该方法包括通过一对二极管将DC偏置电压耦合到MOS晶体管的栅极。

公开(公告)号：US20090295609A1

公开(公告)日：2009-12-03

申请号：US11760743

申请日：2007-06-09

Applicant: T. S. Venkatesh ,  L. Chandrashekar ,  Prasun Kali Bhattacharya ,  Prasenjit Bhowmik ,  C. Srinivasan ,  Mukesh Khatri ,  Sanjeeb Kumar Ghosh ,  Sumanth Chakkirala ,  Sundararajan Krishnan ,  Prakash Easwaran

Inventor： T. S. Venkatesh ,  L. Chandrashekar ,  Prasun Kali Bhattacharya ,  Prasenjit Bhowmik ,  C. Srinivasan ,  Mukesh Khatri ,  Sanjeeb Kumar Ghosh ,  Sumanth Chakkirala ,  Sundararajan Krishnan ,  Prakash Easwaran

IPC: H03M1/00 ,  H03M1/12

CPC classification number: H03M1/0641 ,  H03M1/12

Abstract: A system and method for reducing the power dissipated in an Analog to Digital Converter (ADC). The method includes the steps of: receiving a residue output from a previous phase of a plurality of clock phases where the plurality of clock phases includes a sample-and-hold phase and an amplifying phase for sampling and amplifying an analog input signal respectively, eliminating an effect of load on a residue amplifier when amplifying the residue output to generate an amplified residue output in the amplifying phase, and eliminating an effect of small feedback factor when sampling the amplified residue output in the sample-and-hold phase. Power advantage is achieved by sharing the load on the residue amplifier across the sample-and-hold phase and the amplifying phase rather than being fully present in any one of the clock phases. The present invention also provides a method for reducing the number of comparators used in ADCs.

Abstract translation: 一种降低模数转换器（ADC）功耗的系统和方法。 该方法包括以下步骤：从多个时钟相位的前一相位接收残留输出，其中多个时钟相位包括采样保持相位和用于分别对模拟输入信号进行采样和放大的放大相位，消除 当放大残留物输出时，负载对残留放大器的影响，以在放大阶段产生放大的残留输出，并且在取样和保持阶段中对放大的残留输出进行采样时，消除小的反馈因子的影响。 通过在采样保持阶段和放大阶段共享残留放大器上的负载而不是完全存在于任何一个时钟相位来实现功率优点。 本发明还提供了一种减少ADC中使用的比较器数量的方法。

公开(公告)号：US07548104B2

公开(公告)日：2009-06-16

申请号：US11760784

申请日：2007-06-10

Applicant: Prasenjit Bhowmik ,  Sundararajan Krishnan ,  G. Sriram

Inventor： Prasenjit Bhowmik ,  Sundararajan Krishnan ,  G. Sriram

IPC: H03H11/26

CPC classification number: H03K5/1565 ,  H03H11/265 ,  H03K5/133 ,  H03K2005/00045

Abstract: A delay line including a sequence of identical delay cells with improved gain and in built duty cycle distortion control and a method thereof is disclosed. Each delay cell of the sequence includes a current source, four transistors, and a load capacitor. A gate of the current source receives a voltage bias that controls a delay of the delay cell. A drain of the first transistor is connected to the drain of the current source. The first and second transistor gates receive an input clock signal. The second transistor drain is connected to the source of the current source. The third transistor gate and the load capacitor are also connected to the drain of the current source. The fourth transistor drain is connected to the third transistor drain. The fourth transistor gate is coupled to an output of a second consecutive delay cell for duty cycle distortion control.

Abstract translation: 公开了一种包括具有改善的增益和内置的占空比失真控制的相同延迟单元序列的延迟线及其方法。 序列的每个延迟单元包括电流源，四个晶体管和负载电容器。 电流源的栅极接收控制延迟单元的延迟的电压偏置。 第一晶体管的漏极连接到电流源的漏极。 第一和第二晶体管栅极接收输入时钟信号。 第二晶体管漏极连接到电流源的源极。 第三晶体管栅极和负载电容器也连接到电流源的漏极。 第四晶体管漏极连接到第三晶体管漏极。 第四晶体管栅极耦合到用于占空比失真控制的第二连续延迟单元的输出。

公开(公告)号：US20070285144A1

公开(公告)日：2007-12-13

申请号：US11760784

申请日：2007-06-10

Applicant: Prasenjit BHOWMIK ,  Sundararajan KRISHNAN ,  G. Sriram

Inventor： Prasenjit BHOWMIK ,  Sundararajan KRISHNAN ,  G. Sriram

IPC: H03H11/26

CPC classification number: H03K5/1565 ,  H03H11/265 ,  H03K5/133 ,  H03K2005/00045

Abstract: A delay line including a sequence of identical delay cells with improved gain and in built duty cycle distortion control and a method thereof is disclosed. Each delay cell of the sequence includes a current source, four transistors, and a load capacitor. A gate of the current source receives a voltage bias that controls a delay of the delay cell. A drain of the first transistor is connected to the drain of the current source. The first and second transistor gates receive an input clock signal. The second transistor drain is connected to the source of the current source. The third transistor gate and the load capacitor are also connected to the drain of the current source. The fourth transistor drain is connected to the third transistor drain. The fourth transistor gate is coupled to an output of a second consecutive delay cell for duty cycle distortion control.

Abstract translation: 公开了一种包括具有改善的增益和内置的占空比失真控制的相同延迟单元序列的延迟线及其方法。 序列的每个延迟单元包括电流源，四个晶体管和负载电容器。 电流源的栅极接收控制延迟单元的延迟的电压偏置。 第一晶体管的漏极连接到电流源的漏极。 第一和第二晶体管栅极接收输入时钟信号。 第二晶体管漏极连接到电流源的源极。 第三晶体管栅极和负载电容器也连接到电流源的漏极。 第四晶体管漏极连接到第三晶体管漏极。 第四晶体管栅极耦合到用于占空比失真控制的第二连续延迟单元的输出。