公开(公告)号：US20250106596A1

公开(公告)日：2025-03-27

申请号：US18975422

申请日：2024-12-10

Applicant: QUALCOMM Incorporated

Inventor： Chang-Sik CHOI ,  Kapil GULATI ,  Sudhir Kumar BAGHEL

IPC: H04W4/029 ,  G01S5/02 ,  H04L5/00 ,  H04W4/40 ,  H04W56/00

Abstract: Certain aspects of the present disclosure provide techniques for improving sidelink positioning via messaging between wireless nodes, e.g., roadside service units (RSUs). A method that may be performed by a user equipment (UE) includes receiving a first positioning reference signal (PRS) from a first wireless node, receiving a second PRS from a second wireless node, receiving, from the first wireless node, an estimate of a first clock error component between the first wireless node and the second wireless node, and estimating a position of the UE, based on the first PRS, the second PRS, and the estimate of the first clock error component.

公开(公告)号：US20250106531A1

公开(公告)日：2025-03-27

申请号：US18974248

申请日：2024-12-09

Applicant: QUALCOMM Incorporated

Inventor： Wesley James HOLLAND ,  Micha GALOR GLUSKIN ,  Venkata Ravi Kiran DAYANA ,  Upal MAHBUB ,  Scott BARKER

IPC: H04N23/951 ,  G06T3/4053 ,  H04N23/68

Abstract: Systems and techniques are provided for processing one or more frames. For example, a process can include obtaining a first plurality of frames associated with a first settings domain from an image capture system, wherein the first plurality of frames is captured prior to obtaining a capture input. The process can include obtaining a reference frame associated with a second settings domain from the image capture system, wherein the reference frame is captured proximate to obtaining the capture input. The process can include obtaining a second plurality of frames associated with the second settings domain from the image capture system, wherein the second plurality of frames is captured after the reference frame. The process can include, based on the reference frame, transforming at least a portion of the first plurality of frames to generate a transformed plurality of frames associated with the second settings domain.

公开(公告)号：US20250106086A1

公开(公告)日：2025-03-27

申请号：US18471800

申请日：2023-09-21

Applicant: QUALCOMM Incorporated

Inventor： David YUNUSOV ,  Peer BERGER ,  Amit BAR-OR TILLINGER

IPC: H04L27/26

Abstract: Method and apparatus for reduced signaling overhead in PAPR reduction techniques. The apparatus receives, from a transmitter, a signal comprising a set of overhead bits associated with a PAPR reduction sequence applied to a data signal from the signal, wherein the set of overhead bits are distinct from data symbols corresponding to the data signal. The apparatus decodes the set of overhead bits to identify the PAPR reduction sequence applied to the data signal from the signal. The apparatus removes the PAPR reduction sequence applied to the data signal. The apparatus decodes a remaining set of symbols of the data symbols from the signal, wherein the remaining set of symbols are free of the PAPR reduction sequence.

公开(公告)号：US20250105897A1

公开(公告)日：2025-03-27

申请号：US18728996

申请日：2022-03-31

Applicant: QUALCOMM Incorporated

Inventor： Ahmed ELSHAFIE ,  Kianoush HOSSEINI ,  Yu ZHANG ,  Wanshi CHEN ,  Peter GAAL

IPC: H04B7/06 ,  H04B7/0456 ,  H04W72/25

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a first network node may transmit a first sidelink reference signal (SL-RS) to a second network node. The first network node may receive, from the second network node, a second SL-RS and channel state information (CSI) that is associated with the first (SL-RS). The first network node may determine a (CSI)-related parameter based on the second (SL-RS) and the (CSI). The first network node may transmit, to the second network node, the (CSI)-related parameter or a communication based on the (CSI)-related parameter. Numerous other aspects are described.

公开(公告)号：US20250105867A1

公开(公告)日：2025-03-27

申请号：US18475039

申请日：2023-09-26

Applicant: QUALCOMM Incorporated

Inventor： Aviv REGEV ,  Ronen SHAKED ,  Amit BAR-OR TILLINGER ,  Elad MEIR ,  Yaniv EISTEIN

IPC: H04B1/12

Abstract: Methods, systems, and devices for wireless communications using a singular value decomposition (SVD) combiner precoder are described. The described techniques may enable a network entity to determine which streams of a set of multiple data streams to combine in the SVD combiner precoder to increase a lowest signal-to-noise ratio of the set of multiple data streams, and which streams of the multiple streams to leave separate. The network entity may determine a precoding matrix using a square matrix α, which may allow the network entity to dynamically combine (e.g., or not combine) data streams. The network entity may transmit an indication to a UE indicating which streams the network entity will combine and which streams the network entity will not combine. The UE may accordingly demodulate the non-combined streams with a relatively less complex demodulator and may demodulate the combined streams with a relatively more complex demodulator.

公开(公告)号：US20250105145A1

公开(公告)日：2025-03-27

申请号：US18475080

申请日：2023-09-26

Applicant: QUALCOMM Incorporated

Inventor： Kai LIU ,  Jui-Yi CHIU ,  Jonghae KIM

IPC: H01L23/522 ,  H01L21/768

Abstract: A device comprising a die substrate; a plurality of interconnects located over the die substrate, wherein the plurality of interconnects comprise a first plurality of interconnects comprising a first plurality of via interconnects, wherein the first plurality of interconnects are configured as a first inductor; and a second plurality of interconnects comprising a second plurality of via interconnects, wherein the second plurality of interconnects are configured as a second inductor; wherein the first inductor and the second inductor are intertwined, at least one magnetic layer that surrounds at least part of the first plurality of via interconnects and at least part of the second plurality of via interconnects; and at least one dielectric layer located over the die substrate.

公开(公告)号：US20250103888A1

公开(公告)日：2025-03-27

申请号：US18970538

申请日：2024-12-05

Applicant: QUALCOMM Incorporated

Inventor： Fatemeh SAKI ,  Yinyi GUO ,  Erik VISSER

IPC: G06N3/082 ,  G06V20/10 ,  G10L15/183 ,  G10L15/20 ,  H04L67/00 ,  H04W4/02

Abstract: A device includes one or more processors configured to receive sensor data from one or more sensor devices. The one or more processors are also configured to determine a context of the device based on the sensor data. The one or more processors are further configured to select a model based on the context. The one or more processors are also configured to process an input signal using the model to generate a context-specific output.

公开(公告)号：US20250103545A1

公开(公告)日：2025-03-27

申请号：US18473119

申请日：2023-09-22

Applicant: QUALCOMM Incorporated

Inventor： Hithesh Hassan LEPAKSHA ,  Sharath Kumar NAGILLA ,  Darshan Kumar NANDANWAR

IPC: G06F15/78

Abstract: A method of execution unit (EU) sharing between processor cores is described. The method includes encountering a structural hazard associated with an issued instruction in an instruction queue of a dispatch stage inside an active processor core. The method also includes issuing a request for an idle execution unit of an inactive processor core. The method further includes sending a transaction containing source operands of the issued instruction, and a word address of a result buffer as a destination operand to an allocated EU of the inactive processor core. The method also includes replacing the issued instruction in the instruction queue with a load operation to forward a result of the issued instruction from the result buffer based on the word address.

公开(公告)号：US20250103335A1

公开(公告)日：2025-03-27

申请号：US18475320

申请日：2023-09-27

Applicant: QUALCOMM Incorporated

Inventor： Hithesh Hassan Lepaksha ,  Darshan Kumar Nandanwar ,  Sagar Bamashetti

IPC: G06F9/30

Abstract: A processing unit including a dynamically allocatable vector register file for non-vector instruction processing is disclosed. The processing unit includes an integer execution circuit and integer register file for processing integer instructions. The processing unit also includes a vector execution circuit and a vector register file for processing vector instructions. The integer and vector register files are each sized at design time. A processing unit may be called upon to execute varying workloads that vary between integer and vector operations. Rather than statically dedicating the entire vector register file to vector registers, the processor is configured to dynamically allocate a portion(s) of the vector registers in the vector register file for use in the execution of integer instructions.

公开(公告)号：US20250103293A1

公开(公告)日：2025-03-27

申请号：US18472519

申请日：2023-09-22

Applicant: QUALCOMM Incorporated

Inventor： Francois Ibrahim ATALLAH ,  Yatharth GUPTA

IPC: G06F7/544 ,  G06F5/01

Abstract: A method for multiplication and accumulation includes performing multiplications on a first set of bits and a second set of bits to generate first products, and performing multiplications on a third set of bits and a fourth set of bits to generate second products. The method also includes summing the first products to generate a first sum, changing a bit value of one of the second products, and summing the second products to generate a second sum. The method further includes averaging the first sum and the second sum to obtain an average of the first sum and the second sum, converting the average of the first sum and the second sum into a digital signal, and shifting and adding a one to the digital signal.