公开(公告)号：US20140027864A1

公开(公告)日：2014-01-30

申请号：US13578872

申请日：2012-05-18

申请人： Huilong Zhu ,  Qingqing Liang ,  Huicai Zhong

发明人： Huilong Zhu ,  Qingqing Liang ,  Huicai Zhong

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L29/66659 ,  H01L29/7835

摘要： Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, the method comprises: forming a first shielding layer on a substrate, and forming a first spacer on a sidewall of the first shielding layer; forming one of source and drain regions with the first shielding layer and the first spacer as a mask; forming a second shielding layer on the substrate, and removing the first shielding layer; forming the other of the source and drain regions with the second shielding layer and the first spacer as a mask; removing at least a portion of the first spacer; and forming a gate dielectric layer, and forming a gate conductor in the form of spacer on a sidewall of the second shielding layer or on a sidewall of a remaining portion of the first spacer.

摘要翻译： 公开了半导体装置及其制造方法。 在一个实施例中，该方法包括：在衬底上形成第一屏蔽层，并在第一屏蔽层的侧壁上形成第一间隔物; 用第一屏蔽层和第一间隔件作为掩模形成源区和漏区之一; 在所述基板上形成第二屏蔽层，并移除所述第一屏蔽层; 用第二屏蔽层和第一间隔物作为掩模形成源区和漏区中的另一个; 去除所述第一间隔物的至少一部分; 以及形成栅极电介质层，以及在所述第二屏蔽层的侧壁或所述第一间隔物的剩余部分的侧壁上形成间隔物形式的栅极导体。

公开(公告)号：US20130228893A1

公开(公告)日：2013-09-05

申请号：US13145301

申请日：2011-04-22

申请人： Huicai Zhong ,  Chao Zhao ,  Qingqing Liang

发明人： Huicai Zhong ,  Chao Zhao ,  Qingqing Liang

IPC分类号： H01L21/762 ,  H01L29/02

CPC分类号： H01L21/76224 ,  H01L21/76232 ,  H01L29/02

摘要： A trench isolation structure and a method of forming the same are provided. The trench isolation structure includes: a semiconductor substrate, and trenches formed on the surface of the semiconductor substrate and filled with a dielectric layer, wherein the material of the dielectric layer is a crystalline material. By using the present invention, the size of the divot can be reduced, and device performances can be improved.

摘要翻译： 提供了沟槽隔离结构及其形成方法。 沟槽隔离结构包括：半导体衬底和形成在半导体衬底的表面上并填充有电介质层的沟槽，其中电介质层的材料是结晶材料。 通过使用本发明，可以减小纹路的尺寸，并且可以提高器件性能。

公开(公告)号：US20130037859A1

公开(公告)日：2013-02-14

申请号：US13321852

申请日：2011-08-12

申请人： Huicai Zhong ,  Qingqing Liang ,  Chao Zhao ,  Huilong Zhu

发明人： Huicai Zhong ,  Qingqing Liang ,  Chao Zhao ,  Huilong Zhu

IPC分类号： H01L27/10 ,  H01L21/326 ,  H01L23/522 ,  H01L29/788 ,  H01L29/92 ,  H01L23/525

CPC分类号： H01L23/481 ,  H01L23/525 ,  H01L23/5252 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and a method for programming the same are provided. The semiconductor device comprises: a semiconductor substrate with an interconnect formed therein; a Through-Silicon Via (TSV) penetrating through the semiconductor substrate; and a programmable device which can be switched between on and off states, the TSV being connected to the interconnect by the programmable device. The present invention is beneficial in improving flexibility of TSV application.

摘要翻译： 提供了半导体器件及其编程方法。 半导体器件包括：其中形成有互连的半导体衬底; 穿透半导体衬底的透硅通孔（TSV）; 以及可以在导通和关断状态之间切换的可编程器件，TSV通过可编程器件连接到互连。 本发明有利于提高TSV应用的灵活性。

公开(公告)号：US08367490B2

公开(公告)日：2013-02-05

申请号：US13144182

申请日：2011-03-04

申请人： Huilong Zhu ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

发明人： Huilong Zhu ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L21/84 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/6675 ,  H01L29/78603 ,  H01L29/78648 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present application discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure according to the present invention adjusts a threshold voltage with a common contact, which has a portion outside the source or drain region extending to the back-gate region and provides an electrical contact of the source or drain region and the back-gate region, which leads to a simple manufacturing process, an increased integration level and a lowered manufacture cost. Moreover, the asymmetric design of the back-gate structure further increases the threshold voltage and improves the performance of the device.

摘要翻译： 本申请公开了一种半导体结构及其制造方法。 根据本发明的半导体结构利用公共接触来调节阈值电压，该公共触点具有延伸到背栅极区域的源极或漏极区域之外的部分并且提供源极或漏极区域与背栅极的电接触 区域，这导致简单的制造过程，增加的集成水平和降低的制造成本。 此外，背栅结构的非对称设计进一步增加了阈值电压并提高了器件的性能。

公开(公告)号：US20120290998A1

公开(公告)日：2012-11-15

申请号：US13320291

申请日：2011-04-26

申请人： Qingqing Liang ,  Huilong Zhu ,  Huicai Zhong ,  Meng Li

发明人： Qingqing Liang ,  Huilong Zhu ,  Huicai Zhong ,  Meng Li

IPC分类号： G06F17/50

CPC分类号： H01L22/20

摘要： The present application discloses a device performance prediction method and a device structure optimization method. According to an embodiment of the present invention, a set of structural parameters and/or process parameters for a semiconductor device constitutes a parameter point in a parameter space, and a behavioral model library is established with respect to a plurality of discrete predetermined parameter points in the parameter space, and the predetermined parameter points being associated with their respective performance indicator values in the behavioral model library. The device performance prediction method comprises: inputting a parameter point, called “predicting point”, whose performance indicator value is to be predicted; and if the predicting point has a corresponding record in the behavioral model library, outputting the corresponding performance indicator value as a predicted performance indicator value of the predicting point, or otherwise if there is no record corresponding to the predicting point in the behavioral model library, calculating a predicted performance indicator value of the predicting point by interpolation based on Delaunay triangulation.

摘要翻译： 本申请公开了一种设备性能预测方法和设备结构优化方法。 根据本发明的实施例，用于半导体器件的一组结构参数和/或工艺参数构成参数空间中的参数点，并且针对多个离散的预定参数点建立行为模型库 参数空间以及与行为模型库中其各自的性能指标值相关联的预定参数点。 设备性能预测方法包括：输入要预测其性能指标值的称为预测点的参数点; 并且如果预测点在行为模型库中具有对应的记录，则输出相应的表现指标值作为预测点的预测性能指标值，否则如果没有与行为模型库中的预测点相对应的记录， 通过基于Delaunay三角测量的插值计算预测点的预测性能指标值。

公开(公告)号：US20120281468A1

公开(公告)日：2012-11-08

申请号：US13320331

申请日：2011-08-10

申请人： Qingqing Liang ,  Xiaodong Tong ,  Huicai Zhong ,  Huilong Zhu

发明人： Qingqing Liang ,  Xiaodong Tong ,  Huicai Zhong ,  Huilong Zhu

IPC分类号： G11C11/34

CPC分类号： G11C11/39 ,  G11C17/06 ,  G11C2213/72 ,  G11C2213/74 ,  H01L27/1027

摘要： The present disclosure provides a semiconductor device and a semiconductor memory device. The semiconductor device can be used as a memory cell, and may comprise a first P-type semiconductor layer, a first N-type semiconductor layer, a second P-type semiconductor layer, and a second N-type semiconductor layer arranged in sequence. A first data state may be stored in the semiconductor device by applying a forward bias, which is larger than a punch-through voltage VBO, between the first P-type semiconductor layer and the second N-type semiconductor layer. A second data state may be stored in the semiconductor device by applying a reverse bias, which is approaching to the reverse breakdown region of the semiconductor device, between the first P-type semiconductor layer and the second N-type semiconductor layer. In this way, the semiconductor device may be effectively used for data storage. The semiconductor memory device comprises an array of memory cells consisted of the semiconductor devices.

摘要翻译： 本公开提供了半导体器件和半导体存储器件。 半导体器件可以用作存储单元，并且可以包括依次布置的第一P型半导体层，第一N型半导体层，第二P型半导体层和第二N型半导体层。 第一数据状态可以通过在第一P型半导体层和第二N型半导体层之间施加大于穿通电压VBO的正向偏压来存储在半导体器件中。 第二数据状态可以通过在第一P型半导体层和第二N型半导体层之间施加正在接近半导体器件的反向击穿区域的反向偏压来存储在半导体器件中。 以这种方式，半导体器件可以有效地用于数据存储。 半导体存储器件包括由半导体器件组成的存储器单元的阵列。

公开(公告)号：US20120273886A1

公开(公告)日：2012-11-01

申请号：US13380828

申请日：2011-08-12

申请人： Huicai Zhong ,  Chao Zhao ,  Qingqing Liang

发明人： Huicai Zhong ,  Chao Zhao ,  Qingqing Liang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： An embedded source/drain MOS transistor and a formation method thereof are provided. The embedded source/drain MOS transistor comprises: a semiconductor substrate; a gate structure on the semiconductor substrate; and a source/drain stack embedded in the semiconductor substrate at both sides of the gate structure with an upper surface of the source/drain stack being exposed, wherein the source/drain stack comprises a dielectric layer and a semiconductor layer above the dielectric layer. The present invention can cut off the path for the leakage current from the source region and the drain region to the semiconductor substrate, thereby reducing the leakage current from the source region and the drain region to the semiconductor substrate.

摘要翻译： 提供一种嵌入式源极/漏极MOS晶体管及其形成方法。 嵌入式源极/漏极MOS晶体管包括：半导体衬底; 半导体衬底上的栅极结构; 以及在源极/漏极叠层的上表面被暴露的栅极结构的两侧嵌入在半导体衬底中的源极/漏极堆叠，其中源极/漏极叠层包括电介质层和介电层上方的半导体层。 本发明可以切断从源极区域和漏极区域到半导体衬底的漏电流的路径，从而减少从源极区域和漏极区域到半导体衬底的漏电流。

公开(公告)号：US20120261727A1

公开(公告)日：2012-10-18

申请号：US13380061

申请日：2011-02-27

申请人： Huicai Zhong ,  Qingqing Liang

发明人： Huicai Zhong ,  Qingqing Liang

IPC分类号： H01L29/772 ,  H01L21/768

CPC分类号： H01L29/78 ,  H01L21/76895 ,  H01L21/76897

摘要： A semiconductor device and a method for manufacturing a local interconnect structure for a semiconductor device is provided. The method includes forming removable sacrificial sidewall spacers between sidewall spacers and outer sidewall spacers on two sides of a gate on a semiconductor substrate, and forming contact through-holes at source/drain regions in the local interconnect structure between the sidewall spacer and the outer sidewall spacer on the same side of the gate immediately after removing the sacrificial sidewall spacers. Once the source/drain through-holes are filled with a conductive material to form contact vias, the height of the contact vias shall be same as the height of the gate. The contact through-holes, which establish the electrical connection between a subsequent first layer of metal wiring and the source/drain regions or the gate region at a lower level in the local interconnect structure, shall be made in the same depth.

摘要翻译： 提供半导体器件和用于制造半导体器件的局部互连结构的方法。 该方法包括在半导体衬底上的栅极的两侧上的侧壁间隔件和外侧壁间隔件之间形成可移除的牺牲侧壁间隔件，以及在侧壁间隔件和外侧壁之间的局部互连结构中的源极/漏极区域处形成接触通孔 在去除牺牲侧壁间隔物之后立即在栅极的同一侧上间隔开。 一旦源极/漏极通孔填充有导电材料以形成接触孔，接触孔的高度应与栅极的高度相同。 在本地互连结构中，建立后续的第一金属布线层和源极/漏极区域或较低电平的栅极区域之间的电连接的接触通孔应制成相同的深度。

公开(公告)号：US20120220097A1

公开(公告)日：2012-08-30

申请号：US13061824

申请日：2010-09-26

申请人： Huicai Zhong ,  Qingqing Liang

发明人： Huicai Zhong ,  Qingqing Liang

IPC分类号： H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/3086 ,  H01L21/76897 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7843 ,  H01L29/7848

摘要： A method of manufacturing a semiconductor device is provided, in which after forming a gate stack and a first spacer thereof, a second spacer and a third spacer are formed; and then an opening is formed between the first spacer and the third spacer by removing the second spacer. The range of the formation for the raised active area 220 is limited by forming an opening 214 between the first spacer 208 and the third spacer 212. The raised active area 220 is formed in the opening 214 in a self-aligned manner, so that a better profile of the raised active area 220 may be achieved and the possible shorts between adjacent devices caused by an unlimited manner may be avoided. Moreover, based on such a manufacturing method, it is easy to make the gate electrode 204 to be flushed with the raised active area 220, and is also easy to implement the dual stress nitride process so as to increase the mobility of the device.

摘要翻译： 提供一种制造半导体器件的方法，其中在形成栅极堆叠及其第一间隔物之后，形成第二间隔物和第三间隔物; 然后通过移除第二间隔件在第一间隔件和第三间隔件之间形成开口。 通过在第一间隔件208和第三间隔件212之间形成开口214来限制凸起的有效区域220的形成范围。凸起的有源区域220以自对准的方式形成在开口214中，使得 可以实现凸起的有效区域220的更好的轮廓，并且可以避免由无限制的方式引起的相邻设备之间的可能的短路。 此外，基于这样的制造方法，可以容易地利用凸起的有源区域220冲洗栅电极204，并且也容易实施双应力氮化物工艺，以增加器件的移动性。

公开(公告)号：US20120187491A1

公开(公告)日：2012-07-26

申请号：US13429948

申请日：2012-03-26

申请人： Huilong Zhu ,  Zhijiong Luo ,  Qingqing Liang ,  Haizhou Yin

发明人： Huilong Zhu ,  Zhijiong Luo ,  Qingqing Liang ,  Haizhou Yin

IPC分类号： H01L29/772

CPC分类号： H01L21/187 ,  H01L21/6835 ,  H01L21/84 ,  H01L27/12 ,  H01L29/1083 ,  H01L2221/6835 ,  H01L2221/68368

摘要： A method of forming an electrical device is provided that includes forming at least one semiconductor device on a first semiconductor layer of the SOI substrate. A handling structure is formed contacting the at least one semiconductor device and the first semiconductor layer. A second semiconductor layer and at least a portion of the dielectric layer of the SOI substrate are removed to provide a substantially exposed surface of the first semiconductor layer. A retrograded well may be formed by implanting dopant through the substantially exposed surface of the first semiconductor layer into a first thickness of the semiconductor layer that extends from the substantially exposed surface of the semiconductor layer, wherein a remaining thickness of the semiconductor layer is substantially free of the retrograded well dopant. The retrograded well may be laser annealed.

摘要翻译： 提供一种形成电气装置的方法，包括在SOI衬底的第一半导体层上形成至少一个半导体器件。 形成接触至少一个半导体器件和第一半导体层的处理结构。 去除第二半导体层和SOI衬底的电介质层的至少一部分以提供第一半导体层的基本暴露的表面。 可以通过将掺杂剂通过第一半导体层的基本上暴露的表面注入从半导体层的基本暴露的表面延伸的半导体层的第一厚度来形成退化的阱，其中半导体层的剩余厚度基本上不含 的回归井掺杂剂。 退火井可以进行激光退火。