公开(公告)号：US07023016B2

公开(公告)日：2006-04-04

申请号：US10884083

申请日：2004-07-01

Applicant: Jeong-Young Lee ,  Se-Hwan Yu ,  Sang-Jin Jeon ,  Min-Wook Park

Inventor： Jeong-Young Lee ,  Se-Hwan Yu ,  Sang-Jin Jeon ,  Min-Wook Park

IPC: H01L29/04

CPC classification number: H01L27/12 ,  G02F1/13458 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136231 ,  G02F2001/13629 ,  H01L27/124 ,  H01L27/1288

Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

公开(公告)号：US20050110014A1

公开(公告)日：2005-05-26

申请号：US10922343

申请日：2004-08-19

Applicant: Min-Wook Park ,  Bum-Ki Baek ,  Jeong-Young Lee ,  Kwon-Young Choi ,  Sang-Ki Kwak ,  Sang-Jin Jeon

Inventor： Min-Wook Park ,  Bum-Ki Baek ,  Jeong-Young Lee ,  Kwon-Young Choi ,  Sang-Ki Kwak ,  Sang-Jin Jeon

IPC: G02F1/1339 ,  G02F1/136 ,  G02F1/1368 ,  G09F9/00 ,  G09F9/30 ,  H01L21/00 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L23/52 ,  H01L29/417 ,  H01L29/786 ,  H01L31/036

CPC classification number: H01L29/41733 ,  H01L27/124

Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

公开(公告)号：US08866142B2

公开(公告)日：2014-10-21

申请号：US13177259

申请日：2011-07-06

Applicant: Sang-Jin Jeon ,  Gwang-Bum Ko

Inventor： Sang-Jin Jeon ,  Gwang-Bum Ko

IPC: H01L33/08 ,  H01L27/12

CPC classification number: H01L27/1225 ,  H01L27/124

Abstract: The present invention relates to a display device and a manufacturing method thereof. A display device according to an exemplary embodiment of the present invention includes a substrate including a first surface and a second surface, a first line disposed on the first surface and made of a transparent metal oxide semiconductor, and a first semiconductor disposed on the first surface and made of the transparent metal oxide semiconductor.

Abstract translation: 显示装置及其制造方法技术领域本发明涉及显示装置及其制造方法。 根据本发明的示例性实施例的显示装置包括：基板，包括第一表面和第二表面;第一线，设置在第一表面上，由透明金属氧化物半导体制成，第一半导体设置在第一表面 并由透明金属氧化物半导体制成。

公开(公告)号：US20140011974A1

公开(公告)日：2014-01-09

申请号：US13980860

申请日：2012-01-19

Applicant: Kyung-Seop Noh ,  Nan-Young Lee ,  Won-Hee Kim ,  Sang-Eun An ,  Sang-Jin Jeon ,  Cheon-II Park ,  Choong-Hoon Lee

Inventor： Kyung-Seop Noh ,  Nan-Young Lee ,  Won-Hee Kim ,  Sang-Eun An ,  Sang-Jin Jeon ,  Cheon-II Park ,  Choong-Hoon Lee

IPC: C08F210/16

CPC classification number: C08F295/00 ,  C08F4/64013 ,  C08F4/65904 ,  C08F4/6592 ,  C08F210/16 ,  C08F297/08 ,  C08L23/08 ,  C08L23/0815 ,  C08L23/14 ,  C08L23/142 ,  C08F4/64044 ,  C08F210/00

Abstract: The present description relates to an olefin block copolymer having excellences in elasticity and heat resistance and its preparation method. The olefin block copolymer includes a plurality of blocks or segments, each of which includes an ethylene or propylene repeating unit and an α-olefin repeating unit at different weight fractions. The olefin block copolymer has a density of 0.85 to 0.92 g/cm3, and density X (g/cm3) and TMA (Thermal Mechanical Analysis) value Y (° C.) satisfy a defined relationship.

Abstract translation: 本发明涉及具有优异的弹性和耐热性的烯烃嵌段共聚物及其制备方法。 烯烃嵌段共聚物包括多个嵌段或链段，每个嵌段或链段包括不同重量分数的乙烯或丙烯重复单元和α-烯烃重复单元。 烯烃嵌段共聚物的密度为0.85〜0.92g / cm 3，密度X（g / cm 3）和TMA（热机械分析）值Y（℃）满足规定的关系。

公开(公告)号：US20130296517A1

公开(公告)日：2013-11-07

申请号：US13980870

申请日：2012-01-20

Applicant: Kyung-Seop Noh ,  Won-Hee Kim ,  Nan-Young Lee ,  Sang-Jin Jeon ,  Sang-Eun An

Inventor： Kyung-Seop Noh ,  Won-Hee Kim ,  Nan-Young Lee ,  Sang-Jin Jeon ,  Sang-Eun An

IPC: C08F297/08

CPC classification number: C08F297/083 ,  C08F4/65908 ,  C08F4/6592 ,  C08F210/16 ,  C08F301/00 ,  C08F2410/01 ,  C08F2500/10 ,  C08F4/65904 ,  C08F4/64044 ,  C08F210/14 ,  C08F2500/12 ,  C08F2500/08 ,  C08F2500/03

Abstract: The present description relates to an olefin block copolymer having excellences in elasticity, heat resistance, and processability. The olefin block copolymer includes a plurality of blocks or segments, each of which includes an ethylene or propylene repeating unit and an α-olefin repeating unit at different weight fractions. In the olefin block copolymer, a first derivative of the number Y of short-chain branches (SCBs) per 1,000 carbon atoms of each polymer chain contained in the block copolymer with respect to the molecular weight X of the polymer chains is a negative or positive number of −1.5×10−4 or greater; and the first derivative is from −1.0×10−4 to 1.0×10−4 in the region corresponding to the median of the molecular weight X or above.

Abstract translation: 本发明涉及具有优异的弹性，耐热性和加工性的烯烃嵌段共聚物。 烯烃嵌段共聚物包括多个嵌段或链段，每个嵌段或链段包括不同重量分数的乙烯或丙烯重复单元和α-烯烃重复单元。 在烯烃嵌段共聚物中，相对于聚合物链的分子量X，包含在嵌段共聚物中的每个聚合物链的每1000个碳原子的短链分支数（SCB）的第一个Y的一级导数是负的或正的 数量为-1.5×10-4以上; 在对应于分子量X或更高的中位数的区域中，第一衍生物为-1.0×10-4至1.0×10-4。

公开(公告)号：US08558776B2

公开(公告)日：2013-10-15

申请号：US11999329

申请日：2007-12-04

Applicant: Min-Cheol Lee ,  Hee-Bum Park ,  Yong-Soon Lee ,  Seung-Soo Baek ,  Sang-Jin Jeon

Inventor： Min-Cheol Lee ,  Hee-Bum Park ,  Yong-Soon Lee ,  Seung-Soo Baek ,  Sang-Jin Jeon

IPC: G09G3/36

CPC classification number: G09G3/3611 ,  G09G3/3677 ,  G09G2320/0223

Abstract: In a display panel and a display apparatus having the display panel, the display panel includes array and opposite substrates. The array substrate includes display and peripheral areas. Gate and source lines are formed in the display area. A gate driving part and first and second clock lines are formed in the peripheral area. The gate driving part outputs gate signals to the gate line. The first and second clock lines respectively transmit first and second clock signals to the gate driving part. The opposite substrate is combined with the array substrate and includes a common electrode layer. The common electrode layer has an opening portion patterned to expose the first and second clock lines. The exposed portions of the first and second clock lines have substantially the same area. Thus, delays of the gate signals may be minimized and distortion of the gate signals may be prevented.

Abstract translation: 在具有显示面板的显示面板和显示装置中，显示面板包括阵列和相对的基板。 阵列基板包括显示器和外围区域。 栅极和源极线形成在显示区域中。 在周边区域中形成栅极驱动部分和第一和第二时钟线。 栅极驱动部分将栅极信号输出到栅极线。 第一和第二时钟线分别将第一和第二时钟信号发送到门驱动部分。 相对的衬底与阵列衬底组合并且包括公共电极层。 公共电极层具有图案化以暴露第一和第二时钟线的开口部分。 第一和第二时钟线的暴露部分具有基本上相同的面积。 因此，可以使门信号的延迟最小化并且可以防止门信号的失真。

公开(公告)号：US20120326148A1

公开(公告)日：2012-12-27

申请号：US13465855

申请日：2012-05-07

Applicant: Gwang-Bum KO ,  Sang Jin Jeon

Inventor： Gwang-Bum KO ,  Sang Jin Jeon

IPC: H01L29/786 ,  H01L21/66

CPC classification number: H01L27/124 ,  H01L22/14 ,  H01L22/34

Abstract: A thin film transistor array panel and a manufacturing method therefor. A shorting bar for connecting a thin film transistor with data lines is formed separate from the data lines, and then the data lines and the shorting bar are connected through a connecting member. As a result, all the data lines are floated during manufacture, so that variation in etching speed between data lines does not occur. Since variation in etching speed between the data lines can be prevented, performance deterioration of the transistor caused by a thickness difference in the lower layer of the data line can be prevented, as can resulting deterioration in display quality. Also, the influence of static electricity can be reduced or eliminated. Furthermore, since the data lines and the shorting bar are connected to each other, the generation of static electricity can be prevented or reduced, and quality testing is more readily performed.

Abstract translation: 一种薄膜晶体管阵列面板及其制造方法。 与数据线连接薄膜晶体管的短路棒与数据线分开形成，然后通过连接部件连接数据线和短路棒。 结果，在制造期间所有的数据线都浮起来，从而不会发生数据线之间蚀刻速度的变化。 由于可以防止数据线之间的蚀刻速度的变化，可以防止由数据线的下层的厚度差导致的晶体管的性能劣化，这可能导致显示质量的劣化。 此外，可以减少或消除静电的影响。 此外，由于数据线和短路棒彼此连接，所以可以防止或减少静电的产生，并且更易于进行质量测试。

公开(公告)号：US07960732B2

公开(公告)日：2011-06-14

申请号：US12082495

申请日：2008-04-11

Applicant: Jeong-Young Lee ,  Se-Hwan Yu ,  Sang-Jin Jeon ,  Min-Wook Park

Inventor： Jeong-Young Lee ,  Se-Hwan Yu ,  Sang-Jin Jeon ,  Min-Wook Park

IPC: H01L29/04

CPC classification number: H01L27/12 ,  G02F1/13458 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136231 ,  G02F2001/13629 ,  H01L27/124 ,  H01L27/1288

Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

Abstract translation: 提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在所述下导电膜的第一部分上形成像素电极; 去除下导电膜的第二部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。

公开(公告)号：US20100163880A1

公开(公告)日：2010-07-01

申请号：US12612448

申请日：2009-11-04

Applicant: Sang-Jin JEON

Inventor： Sang-Jin JEON

IPC: H01L33/00 ,  H01L21/70

CPC classification number: G02F1/136204 ,  G02F1/136259 ,  G02F2001/133388 ,  G02F2001/134318 ,  G02F2001/136263 ,  G02F2001/136272 ,  G09G3/3648 ,  G09G2300/0426 ,  G09G2330/04 ,  G09G2330/08 ,  H01L27/124

Abstract: A thin film transistor array panel comprises a repair line disposed in a peripheral area of a display area and being configured to repair when at least one of a gate line and a data line are disconnected, and a detour line disposed in the peripheral area and comprising at least one resistor having higher resistance than a remaining portion of the detour line, wherein both ends of the detour line are connected to the repair line to protect the array panel.

Abstract translation: 薄膜晶体管阵列面板包括设置在显示区域的外围区域中的修复线，并且被配置为当栅极线和数据线中的至少一个断开时进行修复，以及设置在周边区域中的迂回线，并且包括 至少一个电阻器具有比绕行线路的剩余部分更高的电阻，其中绕线的两端连接到修复线以保护阵列面板。

公开(公告)号：US20080191212A1

公开(公告)日：2008-08-14

申请号：US12082495

申请日：2008-04-11

Applicant: Jeong-Young Lee ,  Se-Hwan Yu ,  Sang-Jin Jeon ,  Min-Wook Park

Inventor： Jeong-Young Lee ,  Se-Hwan Yu ,  Sang-Jin Jeon ,  Min-Wook Park

IPC: H01L29/04

CPC classification number: H01L27/12 ,  G02F1/13458 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136231 ,  G02F2001/13629 ,  H01L27/124 ,  H01L27/1288

Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

Abstract translation: 提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在所述下导电膜的第一部分上形成像素电极; 去除下导电膜的第二部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。