公开(公告)号：US5777369A

公开(公告)日：1998-07-07

申请号：US778264

申请日：1997-01-02

Applicant: Shi-Tron Lin ,  Ming-Tsan Yeh ,  Chau-Neng Wu ,  Chi-Hsi Wu

Inventor： Shi-Tron Lin ,  Ming-Tsan Yeh ,  Chau-Neng Wu ,  Chi-Hsi Wu

IPC: G11C11/412 ,  G11C11/419 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: G11C11/4125 ,  G11C11/419 ,  Y10S257/903

Abstract: A bit-line pull-up circuit for an SRAM device which utilizes an improved diffusion structure for enhanced immunity of the SRAM device against electrostatic discharge. The improved diffusion structure includes an undivided diffusion region that serves as a common drain for a plurality of MOS transistors. The undivided diffusion region has at least a pair of recessed diffusion edges formed on opposite sides thereof. The forming of the recessed diffusion edges prevents the so-called electrical field crowding effect and also enhances ESD immunity for the MOS transistor. Further, since the drain diffusion region is an undivided area, an increased number of metal contact windows are provided therein, and at least one of the metal contact windows is arranged substantially between the two recessed diffusion edges. In the event of an electrostatic discharge, this allows the discharge current flowing into the drain to be divided into a greater number of small-magnitude currents flowing to the source.

Abstract translation: 一种用于SRAM器件的位线上拉电路，其利用改进的扩散结构来增强SRAM器件对静电放电的免疫力。 改进的扩散结构包括用作多个MOS晶体管的公共漏极的未分开的扩散区域。 未分开的扩散区域具有形成在其相对侧上的至少一对凹进的扩散边缘。 凹陷扩散边缘的形成防止了所谓的电场拥挤效应，并且还提高了MOS晶体管的ESD抗扰度。 此外，由于漏极扩散区域是不分割的区域，所以在其中设置了增加数量的金属接触窗口，并且金属接触窗口中的至少一个基本上被布置在两个凹进的扩散边缘之间。 在静电放电的情况下，这允许流入漏极的放电电流被分成更大数量的流向源极的小电流电流。

公开(公告)号：US07256461B2

公开(公告)日：2007-08-14

申请号：US10696526

申请日：2003-10-29

Applicant: Shi-Tron Lin ,  Wei-Fan Chen

Inventor： Shi-Tron Lin ,  Wei-Fan Chen

IPC: H01L23/62

CPC classification number: H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a combinded FOX and poly gate structure, for effectively reducing the trigger voltage of a conventional field device, for improving the robustness of a NMOS transistor of a small drive I/O circuit, and for improving the ESD performance of a stack-gate voltage tolerant I/O.

Abstract translation: 本发明提供了一种组合的FOX和多门结构，用于有效地降低常规现场设备的触发电压，以改善小型驱动I / O电路的NMOS晶体管的鲁棒性，并提高堆叠的ESD性能 -gate电压容限I / O。

公开(公告)号：US07137096B2

公开(公告)日：2006-11-14

申请号：US10797998

申请日：2004-03-10

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F2217/78

Abstract: A chip has a power bus, a first metal layer and a plurality of internal electronic circuits. The first metal layer has a plurality of power lines which are substantially parallel and electrically connected to the power bus in parallel for delivering electrical power to the internal electronic circuits. A plurality of metal lines of a second metal layer of the chip are configured by an automatic place and route (APR) process according to the internal electronic circuits, and at least one sparse area is formed on the second metal layer. Later, at least one supply-power area is configured in the sparse area, and is electrically connected to the power bus.

Abstract translation: 芯片具有电源总线，第一金属层和多个内部电子电路。 第一金属层具有多个电力线，其大致平行并且并联电连接到电力总线，用于将电力传递到内部电子电路。 通过根据内部电子电路的自动放置和路由（APR）处理来构成芯片的第二金属层的多个金属线，并且在第二金属层上形成至少一个稀疏区域。 之后，在稀疏区域中配置至少一个供电区域，并与电源总线电连接。

公开(公告)号：US06958896B2

公开(公告)日：2005-10-25

申请号：US10256445

申请日：2002-09-27

Applicant: Shi-Tron Lin ,  Wei-Fan Chen ,  Chen-Hsin Lien

Inventor： Shi-Tron Lin ,  Wei-Fan Chen ,  Chen-Hsin Lien

IPC: H01L27/02 ,  H02H9/04 ,  H02H9/00

CPC classification number: H01L27/0274 ,  H01L2924/0002 ,  H02H9/046 ,  H01L2924/00

Abstract: An early triggered MOSFET ESD protection circuit based on reduction of the trigger voltage is described. A transient negative voltage is generated and applied to a gate of a MOSFET during a positive ESD event. The instant invention improves ESD performance, and is particularly useful for thin gate oxide of 40 Å and less.

Abstract translation: 描述了基于降低触发电压的早期触发MOSFET ESD保护电路。 在正的ESD事件期间产生瞬态负电压并施加到MOSFET的栅极。 本发明改善了ESD性能，并且对于40以下的薄栅极氧化物特别有用。

公开(公告)号：US20050204324A1

公开(公告)日：2005-09-15

申请号：US10797998

申请日：2004-03-10

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F2217/78

Abstract: A chip has a power bus, a first metal layer and a plurality of internal electronic circuits. The first metal layer has a plurality of power lines which are substantially parallel and electrically connected to the power bus in parallel for delivering electrical power to the internal electronic circuits. A plurality of metal lines of a second metal layer of the chip are configured by an automatic place and route (APR) process according to the internal electronic circuits, and at least one sparse area is formed on the second metal layer. Later, at least one supply-power area is configured in the sparse area, and is electrically connected to the power bus.

Abstract translation: 芯片具有电源总线，第一金属层和多个内部电子电路。 第一金属层具有多个电力线，其大致平行并且并联电连接到电力总线，用于将电力传递到内部电子电路。 通过根据内部电子电路的自动放置和路由（APR）处理来构成芯片的第二金属层的多个金属线，并且在第二金属层上形成至少一个稀疏区域。 之后，在稀疏区域中配置至少一个供电区域，并与电源总线电连接。

公开(公告)号：US06850440B2

公开(公告)日：2005-02-01

申请号：US10229925

申请日：2002-08-27

Applicant: Shi-Tron Lin ,  Wei-Fan Chen

Inventor： Shi-Tron Lin ,  Wei-Fan Chen

IPC: G11C16/04 ,  G11C16/12

CPC classification number: G11C16/12 ,  G11C16/0416

Abstract: A method of operating a non-volatile memory device includes providing the non-volatile memory device with a body of first conductivity, a source region of second conductivity, a drain region of second conductivity on the body, and a control gate over the body adjacent to the source and drain regions. A first voltage of first polarity is applied to the control gate. A second voltage of first polarity is applied to the drain region, the second voltage being less than about 5.6 volts. A third voltage of second polarity is applied to the source region.

Abstract translation: 一种操作非易失性存储器件的方法包括：向非易失性存储器件提供具有第一导电体的主体，第二导​​电源的源极区域，以及在主体上具有第二导电性的漏极区域，以及位于主体上方的控制栅极 到源极和漏极区域。 第一极性的第一电压施加到控制栅极。 第一极性的第二电压施加到漏极区，第二电压小于约5.6伏。 第二极性的第三电压被施加到源极区域。

公开(公告)号：US06829722B2

公开(公告)日：2004-12-07

申请号：US09821326

申请日：2001-03-29

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: G06F1100

CPC classification number: G06F11/2733 ,  G06F11/1487

Abstract: A method of processing memory, suitable for loading an executable object code compiled from a source code into the memory that includes defective memory cells. At first, set up a plurality of pre-compiled object codes that correspond to a source code, each pre-compiled object code having at least a skipped-code-address range. Then, test the memory and locate the defective addresses therein. According to the result of the test, the code-loading system selects an executable object that has the matching skipped-code-address range from the pre-compiled object codes, and loads the executable code into the memory. Since the skipped-code-address range covers the defective addresses in the memory, the defective memory cells in the memory won't affect the operation of loading a program.

Abstract translation: 一种处理存储器的方法，适用于将从源代码编译的可执行目标代码加载到包括有缺陷存储器单元的存储器中。 首先，设置与源代码相对应的多个预编译对象代码，每个预编译对象代码至少具有跳过代码地址范围。 然后，测试存储器并找到其中的缺陷地址。 根据测试结果，代码加载系统从预编译对象代码中选择具有匹配的跳过代码地址范围的可执行对象，并将可执行代码加载到存储器中。 由于跳过代码地址范围覆盖存储器中的缺陷地址，所以存储器中的有缺陷的存储单元不会影响加载程序的操作。

公开(公告)号：US06691246B1

公开(公告)日：2004-02-10

申请号：US09690327

申请日：2000-10-16

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: G06F1100

CPC classification number: G06F11/1417

Abstract: A method of processing a partially defective memory for loading a machine code program into a memory device that includes at least one defective memory cell. At first the machine code program is scanned. In addition, a movable code block between two break points, which is ready to be loaded to the defective memory cell of the memory device, is determined. Then the block code is moved to a memory space between a first address and a second address in which there is no defective memory cell. Finally, the moved code block should be linked in the execution sequence with the unmoved portion of the machine code program and the addressing references correlated between the moved code block and the unmoved portion of the machine code program should be modified is and corrected. The resulting machine code program can be properly loaded and executable.

Abstract translation: 一种处理用于将机器代码程序加载到包括至少一个有缺陷的存储器单元的存储器件中的部分缺陷存储器的方法。 首先扫描机器代码程序。 此外，确定准备加载到存储装置的有缺陷的存储单元的两个断点之间的可移动代码块。 然后将块代码移动到第一地址和第二地址之间的存储器空间，其中没有有缺陷的存储器单元。 最后，移动的代码块应该在执行顺序中与机器代码程序的不动部分链接，并且应该修改移动的代码块和机器代码程序的不动部分之间相关的寻址引用。 所得到的机器代码程序可以正确加载并执行。

公开(公告)号：US06653998B2

公开(公告)日：2003-11-25

申请号：US09740223

申请日：2000-12-19

Applicant: Shi-Tron Lin ,  Yung-Peng Hwang

Inventor： Shi-Tron Lin ,  Yung-Peng Hwang

IPC: G09G336

CPC classification number: G09G3/2011 ,  G09G3/3674 ,  G09G3/3685 ,  G09G2310/027 ,  G09G2330/021 ,  H03M1/765

Abstract: A driver circuit for use in driving displays has an input receiving a digital input data having n bits for selecting one of a plurality of voltage levels for driving the circuit. The circuit also has an output, a plurality of digital signal lines coupled to the digital input data, and a plurality of active regions coupled to a first side of the output. Each of the plurality of active regions is coupled to a separate voltage level. The circuit further includes a plurality of pass transistors at a first subset of locations where the plurality of digital signal lines overlap the plurality of active regions, and a plurality of depletion-implanted transistors at a second subset of locations where the plurality of digital signal lines overlap the plurality of active regions. The number of the plurality of digital signal lines on one side of the output can be odd number, such as 2n−1, or can be 2n−2. A plurality of blocking transistors can positioned between the input and selected digital signal lines, with at least one of the digital signal lines being coupled to a gate of each of the blocking transistors for controlling each of the blocking transistors. A level-shifter can also be positioned between selected active regions for one or more digital signal line.

公开(公告)号：US06414361B2

公开(公告)日：2002-07-02

申请号：US09754145

申请日：2001-01-05

Applicant: Shyh-Chyi Wong ,  Shi-Tron Lin

Inventor： Shyh-Chyi Wong ,  Shi-Tron Lin

IPC: H01L2976

CPC classification number: H01L29/66651 ,  H01L21/76224 ,  H01L21/823878

Abstract: An integrated semiconductor device includes a substrate having a buried shallow trench isolation structure and an epitaxial layer disposed over the substrate and the buried shallow trench isolation structure. The epitaxial layer includes a shallow trench isolation structure that extends over the buried shallow trench isolation structure in the substrate to substantially reduce leakage current in the substrate to prevent device latch-up.

Abstract translation: 集成半导体器件包括具有埋入浅沟槽隔离结构的衬底和设置在衬底上的外延层和埋入的浅沟槽隔离结构。 外延层包括浅沟槽隔离结构，其在衬底中的埋入的浅沟槽隔离结构上延伸，以基本上减少衬底中的漏电流以防止器件闭锁。