公开(公告)号：US20060267696A1

公开(公告)日：2006-11-30

申请号：US11496421

申请日：2006-08-01

Applicant: Siavash Fallahi ,  Chun Chen ,  Mark Chambers

Inventor： Siavash Fallahi ,  Chun Chen ,  Mark Chambers

IPC: H03L7/00

CPC classification number: H03L7/18 ,  G11B20/1403 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/0996 ,  H03L7/0998

Abstract: A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.

公开(公告)号：US07005899B2

公开(公告)日：2006-02-28

申请号：US11062495

申请日：2005-02-23

Applicant: Siavash Fallahi ,  Myles Wakayama ,  Pieter Vorenkamp

Inventor： Siavash Fallahi ,  Myles Wakayama ,  Pieter Vorenkamp

IPC: H03K23/00

CPC classification number: H03L7/081 ,  H03K23/68 ,  H03L7/0996 ,  H03L7/18

Abstract: A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a Phase Lock-Loop (PLL), while simultaneously maintaining low jitter. In one embodiment, the invention increases the number of the available clock phases to M and then shifts the output clock phase by one, every K/M cycle. In one aspect of the present invention, this is accomplished by adding a multiplexer (MUX) to the output of the PLL to implement the phase shifting every K/M cycles. In another aspect, the MUX is placed in the feedback loop of the PLL. In one embodiment, a quantizer is used to drive the MUX.

Abstract translation: 一种方法和系统，用于通过任何非整数输出信号频率相对于锁相环（PLL）的参考信号频率进行倍频/除法，同时保持低抖动。 在一个实施例中，本发明将可用时钟相位的数目增加到M，然后每K / M周期将输出时钟相位移位1。 在本发明的一个方面，这通过将多路复用器（MUX）添加到PLL的输出端来实现，以实现每K / M个周期的相移。 在另一方面，MUX被放置在PLL的反馈回路中。 在一个实施例中，使用量化器来驱动MUX。

公开(公告)号：US20050140411A1

公开(公告)日：2005-06-30

申请号：US11062495

申请日：2005-02-23

Applicant: Siavash Fallahi ,  Myles Wakayama ,  Pieter Vorenkamp

Inventor： Siavash Fallahi ,  Myles Wakayama ,  Pieter Vorenkamp

IPC: H03K23/68 ,  H03L7/081 ,  H03L7/099 ,  H03L7/18 ,  H03K3/00

CPC classification number: H03L7/081 ,  H03K23/68 ,  H03L7/0996 ,  H03L7/18

Abstract: A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a Phase Lock-Loop (PLL), while simultaneously maintaining low jitter. In one embodiment, the invention increases the number of the available clock phases to M and then shifts the output clock phase by one, every K/M cycle. In one aspect of the present invention, this is accomplished by adding a multiplexer (MUX) to the output of the PLL to implement the phase shifting every K/M cycles. In another aspect, the MUX is placed in the feedback loop of the PLL. In one embodiment, a quantizer is used to drive the MUX.

公开(公告)号：US06888405B2

公开(公告)日：2005-05-03

申请号：US10372778

申请日：2003-02-26

Applicant: Felix Cheung ,  Kevin T. Chan ,  Siavash Fallahi

Inventor： Felix Cheung ,  Kevin T. Chan ,  Siavash Fallahi

IPC: H03G1/00 ,  H03F1/36

CPC classification number: H03G1/0088

Abstract: A programable gain amplifier (PGA) has an amplifier and a variable resistor that is connected to the output of the amplifier. The variable resistor includes a resistor that is connected to a reference voltage and multiple parallel taps that tap off the resistor. A two-stage switch network having fine stage switches and coarse stage switches connects the resistor taps to an output node of the PGA. The taps and corresponding fine stage switches are arranged into two or more groups, where each group has n-number of fine stage switches and corresponding taps. One terminal of each fine stage switch is connected to the corresponding resistor tap, and the other terminal is connected to an output terminal for the corresponding group. The coarse stage switches select from among the groups of fine stage switches, and connect to the output of the PGA. During operation, one selected tap is connected to the output of the PGA by closing the appropriate fine stage switch and coarse stage switch, where the selected tap defines a selected group of the fine stage switches. Additionally, one fine stage switch is closed in each of the non-selected groups of fine stage switches. In one embodiment, the location of the closed switches in the non-selected groups is the mirror image of the location in an adjacent group. This reduces the transient voltages that occur when tap selection changes from one group to another.

公开(公告)号：US06441655B1

公开(公告)日：2002-08-27

申请号：US09736612

申请日：2000-12-14

Applicant: Siavash Fallahi ,  Myles Wakayama ,  Pieter Vorenkamp

Inventor： Siavash Fallahi ,  Myles Wakayama ,  Pieter Vorenkamp

IPC: H03K2300

CPC classification number: H03L7/081 ,  H03K23/68 ,  H03L7/0996 ,  H03L7/18

Abstract: A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a Phase-Lock-Loop (PLL), while simultaneously maintaining low jitter. In one embodiment, the invention increases the number of the available clock phases to M and then shifts the output clock phase by one, every K/M cycle. In one aspect of the present invention, this is accomplished by adding a multiplexer (MUX) to the output of the PLL to implement the phase shifting every K/M cycles. In another aspect, the MUX is placed in the feedback loop of the PLL. In one embodiment, a quantizer is used to drive the MUX.

Abstract translation: 一种方法和系统，用于通过任何非整数输出信号频率相对于锁相环（PLL）的参考信号频率进行倍频/除法，同时保持低抖动。 在一个实施例中，本发明将可用时钟相位的数目增加到M，然后每K / M周期将输出时钟相位移位1。 在本发明的一个方面，这通过将多路复用器（MUX）添加到PLL的输出端来实现，以实现每K / M个周期的相移。 在另一方面，MUX被放置在PLL的反馈回路中。 在一个实施例中，使用量化器来驱动MUX。

公开(公告)号：US08643218B2

公开(公告)日：2014-02-04

申请号：US11495677

申请日：2006-07-31

Applicant: Siavash Fallahi ,  Kevin Brown

Inventor： Siavash Fallahi ,  Kevin Brown

IPC: H04M1/00

CPC classification number: H04L12/10 ,  H04B3/30 ,  H04B3/44 ,  H04L25/0266

Abstract: A method and apparatus that minimizes saturation caused by power transfer in a communication system transformer, such as a transformer found in a Power-over-Ethernet system. A magnetic flux imbalance causing saturation in the transformer is detected. A compensation current is injected into a winding to minimize the magnetic flux imbalance and saturation.

Abstract translation: 一种使通信系统变压器（例如在以太网供电系统中发现的变压器）中的功率传递引起的饱和度最小化的方法和装置。 检测变压器饱和的磁通不平衡。 将补偿电流注入到绕组中以最小化磁通不平衡和饱和度。

公开(公告)号：US20120223765A1

公开(公告)日：2012-09-06

申请号：US13037462

申请日：2011-03-01

Applicant: Jingguang Wang ,  Derek Tam ,  Mark Berman ,  Siavash Fallahi

Inventor： Jingguang Wang ,  Derek Tam ,  Mark Berman ,  Siavash Fallahi

IPC: H03K3/01

CPC classification number: G06F1/3206

Abstract: While an IC chip is in idle mode with no power being supplied to the IC chip, the IC chip may be operable to detect a signal pulse received by the IC chip using energy associated with the signal pulse. The IC chip may be operable to control a control signal for a power switch using the energy associated with the signal pulse. The power switch may allow power to be provided to the IC chip based on the control signal. The IC chip may comprise a pulse detector, a latch circuit and an ON/OFF logic circuit within the IC chip. While the IC chip is fully powered and communication with a partner chip is finished, the IC chip may be operable to control the control signal to turn off the power switch for powering down the IC chip based on a turn-off signal.

Abstract translation: 虽然IC芯片处于空闲模式，而没有向IC芯片提供电力，但是IC芯片可以用于使用与信号脉冲相关联的能量来检测由IC芯片接收的信号脉冲。 IC芯片可以用于使用与信号脉冲相关联的能量来控制功率开关的控制信号。 电源开关可以基于控制信号来允许向IC芯片提供电力。 IC芯片可以包括IC芯片内的脉冲检测器，锁存电路和ON / OFF逻辑电路。 当IC芯片完全供电并且与伙伴芯片的通信完成时，IC芯片可以可操作地控制控制信号以关闭电源开关，以基于关断信号对IC芯片供电。

公开(公告)号：US20090080413A1

公开(公告)日：2009-03-26

申请号：US12277981

申请日：2008-11-25

Applicant: Siavash Fallahi ,  Lin Able Chu

Inventor： Siavash Fallahi ,  Lin Able Chu

IPC: H04L12/66

CPC classification number: H03H7/06 ,  H03H7/075 ,  H03H7/1758 ,  H03H7/38 ,  H03H7/425 ,  H04M1/2535 ,  Y10S379/90 ,  Y10T307/832

Abstract: An Internet Protocol (IP) telephone has a constant impedance filter that is capable of being continuously attached to the physical layer of a computer chip in the IP telephone. The constant impedance filter is located outside the physical layer and is connected to a relay on the physical layer. The relay is configured using native FET devices, which are normally conductive without a supply voltage. Therefore, the relay is capable of operating during the discovery mode of IP telephone operation, where no power is applied to the substrate. Rectifier circuits rectify an incoming signal during discovery mode, and apply the rectified signal to the gate of the relay to improve conductivity of the relay. This allows for faster detection of the IP telephone during discovery mode. During normal operation mode, voltage is applied to the physical layer, and the relay is opened by grounding the native devices. Also, during the normal operation mode, any signal coming from the constant impedance filter is terminated in a switchable termination resistor that is also disposed on the physical layer.

Abstract translation: 互联网协议（IP）电话具有恒定阻抗滤波器，其能够连续地附着到IP电话中的计算机芯片的物理层。 恒定阻抗滤波器位于物理层之外，并连接到物理层上的继电器。 继电器使用天然FET器件进行配置，该器件通常在没有电源电压的情况下导通。 因此，继电器能够在IP电话操作的发现模式下操作，其中没有电力施加到基板。 整流电路在发现模式下对输入信号进行整流，并将整流信号施加到继电器的门，以提高继电器的导通性。 这允许在发现模式期间更快地检测IP电话。 在正常工作模式下，电压施加到物理层，继电器通过对本机进行接地而打开。 此外，在正常操作模式期间，来自恒定阻抗滤波器的任何信号终止于也设置在物理层上的可切换终端电阻器中。

公开(公告)号：US07508272B2

公开(公告)日：2009-03-24

申请号：US11902604

申请日：2007-09-24

Applicant: Siavash Fallahi ,  Chun Ying Chen ,  Mark J. Chambers

Inventor： Siavash Fallahi ,  Chun Ying Chen ,  Mark J. Chambers

IPC: H03L7/00

CPC classification number: H03L7/18 ,  G11B20/1403 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/0996 ,  H03L7/0998

Abstract: A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.

Abstract translation: 一种用于产生具有用于接收参考信号的输入端的多个合成时钟的系统，耦合到所述输入信号端的锁相环电路，其中所述锁相环电路能够产生频率锁定到所述输入信号的多个输出信号 参考信号并且具有多个不同的相位，耦合到锁相环电路的相位旋转器，其中相位旋转器产生更大的多个相位。

公开(公告)号：US20080018406A1

公开(公告)日：2008-01-24

申请号：US11902604

申请日：2007-09-24

Applicant: Siavash Fallahi ,  Chun Chen ,  Mark Chambers

Inventor： Siavash Fallahi ,  Chun Chen ,  Mark Chambers

IPC: H03L7/00

CPC classification number: H03L7/18 ,  G11B20/1403 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/0996 ,  H03L7/0998

Abstract: A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.

Abstract translation: 一种用于产生具有用于接收参考信号的输入端的多个合成时钟的系统，耦合到所述输入信号端的锁相环电路，其中所述锁相环电路能够产生频率锁定到所述输入信号的多个输出信号 参考信号并且具有多个不同的相位，耦合到锁相环电路的相位旋转器，其中相位旋转器产生更大的多个相位。