公开(公告)号：US07814401B2

公开(公告)日：2010-10-12

申请号：US11642708

申请日：2006-12-21

申请人： Idan Alrod ,  Eran Sharon ,  Simon Litsyn ,  Menahem Lasser

发明人： Idan Alrod ,  Eran Sharon ,  Simon Litsyn ,  Menahem Lasser

IPC分类号： H03M13/00

CPC分类号： G11C11/5642 ,  G06F11/1068 ,  G06F11/1072 ,  G11C16/26 ,  G11C2211/5634

摘要： To read one or more flash memory cells, the threshold voltage of each cell is compared to at least one integral reference voltage and to at least one fractional reference voltage. Based on the comparisons, a respective estimated probability measure of each bit of an original bit pattern of each cell is calculated. This provides a plurality of estimated probability measures. Based at least in part on at least two of the estimated probability measures, respective original bit patterns of the cells are estimated. Preferably, the estimated probability measures are initial probability measures that are transformed to final probability measures under the constraint that the bit pattern(s) (collectively) is/are a member of a candidate set, e.g. a set of codewords.

摘要翻译： 为了读取一个或多个闪存单元，将每个单元的阈值电压与至少一个积分参考电压和至少一个分数参考电压进行比较。 基于比较，计算每个单元的原始比特模式的每个比特的相应估计概率测量。 这提供了多个估计的概率度量。 至少部分地基于估计的概率测量中的至少两个，估计小区的各自的原始比特模式。 优选地，估计的概率度量是在比特模式（统称为）是候选集合的成员的约束下被转换为最终概率测量的初始概率测量，例如。 一组码字。

公开(公告)号：US07643342B2

公开(公告)日：2010-01-05

申请号：US12045733

申请日：2008-03-11

申请人： Simon Litsyn ,  Eran Sharon ,  Idan Alrod

发明人： Simon Litsyn ,  Eran Sharon ,  Idan Alrod

IPC分类号： G11C11/34 ,  G11C16/06 ,  G06F12/00 ,  G06F13/00

CPC分类号： G11C16/10 ,  G06F11/1072 ,  G11C7/1006 ,  G11C11/56 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/34 ,  G11C29/42 ,  G11C2211/5641

摘要： To store a plurality of input bits, the bits are mapped to a corresponding programmed state of one or more memory cells and the cell(s) is/are programmed to that corresponding programmed state. The mapping may be many-to-one or may be an “into” generalized Gray mapping. The cell(s) is/are read to provide a read state value that is transformed into a plurality of output bits, for example by maximum likelihood decoding or by mapping the read state value into a plurality of soft bits and then decoding the soft bits.

摘要翻译： 为了存储多个输入位，这些位被映射到一个或多个存储器单元的相应的编程状态，并且单元被编程为相应的编程状态。 映射可以是多对一的或者可以是“到”广义灰色映射。 读取单元以提供被转换成多个输出位的读取状态值，例如通过最大似然解码或通过将读取状态值映射到多个软比特中，然后解码软比特 。

公开(公告)号：US20090319868A1

公开(公告)日：2009-12-24

申请号：US12407098

申请日：2009-03-19

申请人： Eran SHARON ,  Idan ALROD ,  Simon LITSYN

发明人： Eran SHARON ,  Idan ALROD ,  Simon LITSYN

IPC分类号： H03M13/05 ,  G06F12/02 ,  G06F11/10

CPC分类号： G11C16/26 ,  G06F11/1068 ,  G11C11/5642

摘要： To read a plurality of memory cells, each cell is assigned to a respective cell population. A respective value of an operational parameter of each cell is measured. Each cell is assigned an a-priori metric based at least in part on one or more CVD parameter values of the cell's population. The a-priori metrics are decoded. Based at least in part on the resulting a-posteriori metrics, the CVD parameter values are corrected, without repeating the measurements of the cell operational parameter values. The operational parameter values are indicative of bit patterns stored in the cells, and the correction of the CVD parameter values is constrained by requiring the bit patterns collectively to be a valid codeword.

摘要翻译： 为了读取多个存储单元，将每个单元分配给相应的单元群。 测量每个单元的操作参数的相应值。 至少部分地基于单元格群体的一个或多个CVD参数值，为每个单元分配先验度量。 先验先验度量被解码。 至少部分地基于得到的后验度量，校正CVD参数值，而不重复单元操作参数值的测量。 操作参数值表示存储在单元中的位模式，并且通过要求位图集合成为有效代码字来限制CVD参数值的校正。

公开(公告)号：US20090319858A1

公开(公告)日：2009-12-24

申请号：US12404308

申请日：2009-03-15

申请人： Eran SHARON ,  Simon Litsyn ,  Idan Alrod

发明人： Eran SHARON ,  Simon Litsyn ,  Idan Alrod

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/1131 ,  H03M13/1114 ,  H03M13/6505 ,  H03M13/6588

摘要： To decode a manifestation of a codeword in which K information bits are encoded as N>K codeword bits, messages are exchanged between N bit nodes and N−K check nodes. During computation, messages are expressed with a full message length greater than two bits. In each iteration, representations of at least some of the exchanged messages are stored. For at least one node, if representations of messages sent from that node are stored, then the representation of one or more of the messages is stored using at least two bits but using fewer bits than the full message length, and the representation of one other message is stored with full message length. Preferably, the messages that are stored using fewer bits than the full message length are messages sent from check nodes.

摘要翻译： 为了解码其中K个信息比特被编码为N> K个码字比特的码字的表现，在N个比特节点和N-K个校验节点之间交换消息。 在计算期间，消息以大于两位的完整消息长度表示。 在每次迭代中，存储至少一些交换的消息的表示。 对于至少一个节点，如果存储了从该节点发送的消息的表示，则使用至少两个比特来存储一个或多个消息的表示，但是使用比全消息长度少的比特，并且另一个的表示 消息以完整的消息长度存储。 优选地，使用比完整消息长度少的位来存储的消息是从校验节点发送的消息。

公开(公告)号：US20090034649A1

公开(公告)日：2009-02-05

申请号：US11458691

申请日：2006-07-20

申请人： Simon Litsyn ,  Alexander Shpunt

发明人： Simon Litsyn ,  Alexander Shpunt

IPC分类号： H04L27/00

CPC分类号： H04L27/2615

摘要： A plurality of bits is transmitted by partitioning the bits among n subsets; encoding each subset as a respective symbol; selecting a balancing vector, in accordance with the symbols, from a set of size 2p of codewords of length n in {−1,1}; multiplying each symbol by a corresponding element of the balancing vector; and transmitting the symbols substantially simultaneously. Preferably, the set of codewords has a strength of at most about 2 ln └i┘. The balancing vector is selected either deterministically or probabilistically.

摘要翻译： 通过划分n个子集中的比特来发送多个比特; 将每个子集编码为相应的符号; 从{-1,1}中的长度为n的码字的大小2p的集合中，根据符号选择平衡向量; 将每个符号乘以平衡矢量的相应元素; 并且基本上同时发送符号。 优选地，所述码字集合的强度至多约为2π。 选择平衡向量确定性或概率。

公开(公告)号：US20080010581A1

公开(公告)日：2008-01-10

申请号：US11607945

申请日：2006-12-04

申请人： Idan Alrod ,  Eran Sharon ,  Simon Litsyn

发明人： Idan Alrod ,  Eran Sharon ,  Simon Litsyn

IPC分类号： G11C29/00

CPC分类号： G11C11/5642 ,  G06F11/1072 ,  G11C29/00

摘要： Data are encoded as a systematic or nonsystematic codeword that is stored in a memory such as a flash memory. A representation of the codeword is read from the memory. A plurality of bits related to the representation of the codeword is decoded iteratively. The plurality of bits could be, for example, part or all of the representation of the codeword itself or part or all of the results of preliminary processing of part or all of the representation of the codeword.

摘要翻译： 数据被编码为存储在诸如闪存之类的存储器中的系统或非系统码字。 从存储器读取码字的表示。 与代码字的表示相关的多个位被迭代地解码。 多个比特可以是例如代码字本身的表示的部分或全部，或部分或全部代码字表示的初步处理结果的部分或全部。

公开(公告)号：US20070283227A1

公开(公告)日：2007-12-06

申请号：US11528556

申请日：2006-09-28

申请人： Eran Sharon ,  Idan Alrod ,  Simon Litsyn

发明人： Eran Sharon ,  Idan Alrod ,  Simon Litsyn

IPC分类号： H03M13/00

CPC分类号： H03M13/3738 ,  H03M13/3707 ,  H03M13/6502 ,  H03M13/6511

摘要： A representation of a codeword is decoded by applying a first decoder of the codeword to the representation of the codeword. If applying the first decoder fails to decode the representation of the codeword then a second decoder of the codeword is applied to the representation of the codeword. Preferably, applying the first decoder consumes less power and is faster than applying the second decoder. Data are ported by encoding the data as a codeword, exporting the codeword to a corrupting medium, importing a representation of the codeword, and applying a first decoder to the representation of the codeword. If applying the first decoder fails to decode the representation of the codeword then a second decoder of the codeword is applied to the representation of the codeword.

摘要翻译： 通过将码字的第一解码器应用于码字的表示来解码码字的表示。 如果应用第一解码器不能解码码字的表示，则码字的第二解码器被应用于码字的表示。 优选地，应用第一解码器消耗较少的功率并且比应用第二解码器更快。 数据通过将数据编码为码字来移植，将码字导出到破坏性介质，导入码字的表示，以及将第一解码器应用于码字的表示。 如果应用第一解码器不能解码码字的表示，则码字的第二解码器被应用于码字的表示。

公开(公告)号：US09424178B2

公开(公告)日：2016-08-23

申请号：US13806007

申请日：2011-06-21

申请人： Eran Sharon ,  Idan Alrod ,  Simon Litsyn

发明人： Eran Sharon ,  Idan Alrod ,  Simon Litsyn

IPC分类号： G06F12/02 ,  H03M13/05 ,  G06F11/10 ,  G11C11/56 ,  G11C16/10 ,  G11C7/10 ,  G11C29/00

CPC分类号： G06F12/0246 ,  G06F11/1072 ,  G06F11/1076 ,  G11C7/1006 ,  G11C11/5628 ,  G11C16/10 ,  G11C29/00 ,  G11C2211/5641 ,  H03M13/05

摘要： A method and system for optimizing flash memory without dedicated parity area and with reduced array size. The memory size of a multi level cell (MLC) flash is reduced and controller operation is simplified. Simplified operation includes the controller being able to program each host data page to an integer number of flash pages. A maximal available information bits per cell (IBPC) is maintained in a flash device while also maximizing the programming throughput of the flash. Features include the ability to dynamically select which number of cell states is used by flash memory cells.

摘要翻译： 一种用于优化闪存而没有专用奇偶校验区和减小阵列大小的方法和系统。 多级单元（MLC）闪存的存储器容量减小，控制器操作简化。 简化操作包括控制器能够将每个主机数据页面编程为整数个闪存页面。 在闪存设备中维护每个单元（IBPC）的最大可用信息位，同时还使闪存的编程吞吐量最大化。 特性包括动态选择闪存单元使用哪些单元状态的能力。

公开(公告)号：US09070453B2

公开(公告)日：2015-06-30

申请号：US13086408

申请日：2011-04-14

申请人： Eran Sharon ,  Idan Alrod ,  Simon Litsyn ,  Ishai Ilani

发明人： Eran Sharon ,  Idan Alrod ,  Simon Litsyn ,  Ishai Ilani

IPC分类号： G06F12/02 ,  G11C16/10 ,  G11C11/56 ,  G11C16/34

CPC分类号： G11C16/102 ,  G06F12/02 ,  G11C11/5628 ,  G11C16/349

摘要： To store, successively, in a plurality of memory cells, first and second pluralities of input bits that are equal in number, a first transformation transforms the first input bits into a first plurality of transformed bits. A first portion of the cells is programmed to store the first transformed bits according to a mapping of bit sequences to cell levels, but, if the first transformation has a variable output length, only if there are few enough first transformed bits to fit in the first cell portion. Then, without erasing a second cell portion that includes the first portion, if respective levels of the cells of the second portion, that represent a second plurality of transformed bits obtained by a second transformation of the second input bits, according to the mapping, are accessible from the current cell levels, the second portion is so programmed to store the second transformed bits.

摘要翻译： 为了顺次地在多个存储单元中存储数量相等的第一和第二多个输入位，第一变换将第一输入位变换为第一多个变换位。 单元的第一部分被编程为根据位序列到单元级别的映射来存储第一变换的位，但是如果第一变换具有可变的输出长度，则只有当足够少的第一变换位适合于 第一细胞部分。 然后，在不擦除包括第一部分的第二单元部分的情况下，如果根据映射，表示通过第二输入位的第二变换获得的第二多个变换位的第二部分的单元的各个级别是 从当前单元级可访问，第二部分被编程为存储第二转换位。

公开(公告)号：US20140013033A1

公开(公告)日：2014-01-09

申请号：US13806007

申请日：2011-06-21

申请人： Eran Sharon ,  Idan Alrod ,  Simon Litsyn

发明人： Eran Sharon ,  Idan Alrod ,  Simon Litsyn

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F11/1072 ,  G06F11/1076 ,  G11C7/1006 ,  G11C11/5628 ,  G11C16/10 ,  G11C29/00 ,  G11C2211/5641 ,  H03M13/05

摘要： A method and system for optimizing flash memory without dedicated parity area and with reduced array size. The memory size of a multi level cell (MLC) flash is reduced and controller operation is simplified. Simplified operation includes the controller being able to program each host data page to an integer number of flash pages. A maximal available information bits per cell (IBPC) is maintained in a flash device while also maximizing the programming throughput of the flash. Features include the ability to dynamically select which number of cell states is used by flash memory cells.

摘要翻译： 一种用于优化闪存而没有专用奇偶校验区和减小阵列大小的方法和系统。 多级单元（MLC）闪存的存储器容量减小，控制器操作简化。 简化操作包括控制器能够将每个主机数据页面编程为整数个闪存页面。 在闪存设备中维护每个单元（IBPC）的最大可用信息位，同时还使闪存的编程吞吐量最大化。 特性包括动态选择闪存单元使用哪些单元状态的能力。