公开(公告)号：US20090150654A1

公开(公告)日：2009-06-11

申请号：US11952858

申请日：2007-12-07

Applicant: Stuart Oberman ,  Ming Y. Siu ,  David C. Tannenbaum

Inventor： Stuart Oberman ,  Ming Y. Siu ,  David C. Tannenbaum

IPC: G06F9/302

CPC classification number: G06F9/30014 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/3893 ,  G06T1/20

Abstract: A functional unit is added to a graphics processor to provide direct support for double-precision arithmetic, in addition to the single-precision functional units used for rendering. The double-precision functional unit can execute a number of different operations, including fused multiply-add, on double-precision inputs using data paths and/or logic circuits that are at least double-precision width. The double-precision and single-precision functional units can be controlled by a shared instruction issue circuit, and the number of copies of the double-precision functional unit included in a core can be less than the number of copies of the single-precision functional units, thereby reducing the effect of adding support for double-precision on chip area.

Abstract translation: 除了用于渲染的单精度功能单元之外，功能单元被添加到图形处理器以提供对双精度算术的直接支持。 双精度功能单元可以使用至少双精度宽度的数据路径和/或逻辑电路在双精度输入上执行多种不同的操作，包括融合乘法运算。 双精度和单精度功能单元可以由共享指令发出电路控制，核心中包含的双精度功能单元的份数可以小于单精度功能的副本数 单位，从而降低了对双精度芯片面积的支持的影响。

公开(公告)号：US20080080548A1

公开(公告)日：2008-04-03

申请号：US11871105

申请日：2007-10-11

Applicant: Rodney Mullendore ,  Stuart Oberman ,  Anil Mehta ,  Keith Schakel ,  Kamran Malik

Inventor： Rodney Mullendore ,  Stuart Oberman ,  Anil Mehta ,  Keith Schakel ,  Kamran Malik

IPC: H04B7/212

CPC classification number: H04L49/103 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/351 ,  H04L49/357 ,  H04Q11/04 ,  H04Q2213/13292 ,  H04Q2213/13296 ,  H04Q2213/13332 ,  H04Q2213/13389

Abstract: A system and method for managing the allocation of Time Division Multiplexing (TDM) timeslots in a network switch. The network switch may use a TDM cycle comprising multiple timeslots to manage shared resources and to schedule data ingress and egress through the ports of the current configuration, wherein each port is assigned one or more timeslots. The network switch may be reprogrammed to support one of multiple timeslot assignment schemes for one of multiple port configurations. The network switch may support configurations with varying numbers of ports, e.g. 8- and 16-port configurations. A network switch may also support configurations where two or more ports are combined to form one port, for example, a 2 Gbs Fibre Channel port. To meet the requirements of the various configurations, the timeslot assignment scheme may be reprogrammed to meet the scheduling requirements of each of the possible port configurations.

Abstract translation: 一种用于管理网络交换机中时分多路复用（TDM）时隙分配的系统和方法。 网络交换机可以使用包括多个时隙的TDM周期来管理共享资源，并且通过当前配置的端口来调度数据入口和出口，其中每个端口被分配一个或多个时隙。 网络交换机可以被重新编程以支持多个端口配置之一的多个时隙分配方案之一。 网络交换机可以支持具有不同数量端口的配置，例如， 8和16端口配置。 网络交换机还可以支持将两个或多个端口组合以形成一个端口（例如，2Gbs光纤通道端口）的配置。 为了满足各种配置的要求，时隙分配方案可以被重新编程以满足每个可能的端口配置的调度要求。

公开(公告)号：US06381625B2

公开(公告)日：2002-04-30

申请号：US09782474

申请日：2001-02-12

Applicant: Stuart Oberman ,  Norbert Juffa ,  Ming Siu ,  Frederick D Weber ,  Ravikrishna Cherukuri

Inventor： Stuart Oberman ,  Norbert Juffa ,  Ming Siu ,  Frederick D Weber ,  Ravikrishna Cherukuri

IPC: G06F7552

CPC classification number: G06F7/53 ,  G06F7/4991 ,  G06F7/49936 ,  G06F7/49963 ,  G06F7/49994 ,  G06F7/5338 ,  G06F7/5443 ,  G06F9/30036 ,  G06F9/3017 ,  G06F9/3804 ,  G06F9/3885 ,  G06F17/16 ,  G06F2207/3828

Abstract: A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated and used to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components. The multiplier may also be configured to sum the products of the vector components to form the vector dot product. The final product may be output in segments so as to require fewer bus lines. The segments may be rounded by adding a rounding constant. Rounding and normalization may be performed in two paths, one assuming an overflow will occur, the other assuming no overflow will occur. The multiplier may also be configured to perform iterative calculations to evaluate constant powers of an operand. Intermediate products that are formed may be rounded and normalized in two paths and then compressed and stored for use in the next iteration. An adjustment constant may also be added to increase the frequency of exactly rounded results.

Abstract translation: 公开了能够执行有符号和无符号标量和矢量乘法的乘法器。 乘法器配置为以标量或压缩向量形式接收带符号或无符号乘数和被乘数操作数。 可以计算乘数和被乘数操作数的有效符号，并用于根据布斯算法创建和选择多个部分乘积。 一旦创建并选择了部分产品，就可以对它们进行求和并输出结果。 结果可能是有符号或无符号的，可能表示向量或标量。 当执行向量乘法时，乘法器可以被配置为产生和选择部分乘积，以便有效地隔离每对向量分量的乘法过程。 乘法器还可以被配置为对矢量分量的乘积求和以形成向量点积。 最终产品可以分段输出，以便需要更少的总线。 可以通过添加舍入常数来对段进行舍入。 可以在两个路径中执行舍入和归一化，一个假设将发生溢出，另一个假设不会发生溢出。 乘法器还可以被配置为执行迭代计算以评估操作数的恒定功率。 形成的中间产品可以在两个路径中进行圆化和归一化，然后压缩并存储以用于下一次迭代。 还可以添加调整常数以增加精确舍入结果的频率。

公开(公告)号：US08051123B1

公开(公告)日：2011-11-01

申请号：US11611800

申请日：2006-12-15

Applicant: Stuart Oberman ,  Ming Y. Siu

Inventor： Stuart Oberman ,  Ming Y. Siu

IPC: G06F7/38

CPC classification number: G06F7/38 ,  G06F7/483 ,  G06F7/5443 ,  G06F7/57

Abstract: A multipurpose arithmetic functional unit selectively performs planar attribute interpolation, unary function approximation, double-precision arithmetic, and/or arbitrary filtering functions such as texture filtering, bilinear filtering, or anisotropic filtering by iterating through a multi-step multiplication operation with partial products (partial results) accumulated in an accumulation register. Shared multiplier and adder circuits are advantageously used to implement the product and sum operations for unary function approximation and planar interpolation; the same multipliers and adders are also leveraged to implement double-precision multiplication and addition.

Abstract translation: 多用途算术功能单元通过迭代通过部分乘积的多步乘法运算来选择性地执行平面属性插值，一元函数近似，双精度算术和/或任意滤波函数，例如纹理滤波，双线性滤波或各向异性滤波， 部分结果）积累在累积寄存器中。 共享乘法器和加法器电路有利地用于实现一元函数近似和平面内插的乘积和求和运算; 同样的乘法器和加法器也被用来实现双精度乘法和加法。

公开(公告)号：US20060101243A1

公开(公告)日：2006-05-11

申请号：US10985695

申请日：2004-11-10

Applicant: Ming Siu ,  Stuart Oberman

Inventor： Ming Siu ,  Stuart Oberman

IPC: G06F9/44

CPC classification number: G06F7/483 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/3875 ,  G06F9/3885

Abstract: A multipurpose functional unit is configurable to support a number of operations including multiply-add and comparison testing operations, as well as other integer and/or floating-point arithmetic operations, Boolean operations, and format conversion operations.

Abstract translation: 多用途功能单元可配置为支持多种操作，包括乘法和比较测试操作，以及其他整数和/或浮点运算，布尔运算和格式转换操作。

公开(公告)号：US06397238B2

公开(公告)日：2002-05-28

申请号：US09782475

申请日：2001-02-12

Applicant: Stuart Oberman ,  Norbert Juffa ,  Ming Siu ,  Frederick D Weber ,  Ravikrishna Cherukuri

Inventor： Stuart Oberman ,  Norbert Juffa ,  Ming Siu ,  Frederick D Weber ,  Ravikrishna Cherukuri

IPC: G06F752

CPC classification number: G06F7/53 ,  G06F7/4991 ,  G06F7/49936 ,  G06F7/49963 ,  G06F7/49994 ,  G06F7/5338 ,  G06F7/5443 ,  G06F9/30036 ,  G06F9/3017 ,  G06F9/3804 ,  G06F9/3885 ,  G06F17/16 ,  G06F2207/3828

Abstract: A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated and used to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components. The multiplier may also be configured to sum the products of the vector components to form the vector dot product. The final product may be output in segments so as to require fewer bus lines. The segments may be rounded by adding a rounding constant. Rounding and normalization may be performed in two paths, one assuming an overflow will occur, the other assuming no overflow will occur. The multiplier may also be configured to perform iterative calculations to evaluate constant powers of an operand. Intermediate products that are formed may be rounded and normalized in two paths and then compressed and stored for use in the next iteration. An adjustment constant may also be added to increase the frequency of exactly rounded results.

Abstract translation: 公开了能够执行有符号和无符号标量和矢量乘法的乘法器。 乘法器配置为以标量或压缩向量形式接收带符号或无符号乘数和被乘数操作数。 可以计算乘数和被乘数操作数的有效符号，并用于根据布斯算法创建和选择多个部分乘积。 一旦创建并选择了部分产品，就可以对它们进行求和并输出结果。 结果可能是有符号或无符号的，可能表示向量或标量。 当执行向量乘法时，乘法器可以被配置为产生和选择部分乘积，以便有效地隔离每对向量分量的乘法过程。 乘法器还可以被配置为对矢量分量的乘积求和以形成向量点积。 最终产品可以分段输出，以便需要更少的总线。 可以通过添加舍入常数来对段进行舍入。 可以在两个路径中执行舍入和归一化，一个假设将发生溢出，另一个假设不会发生溢出。 乘法器还可以被配置为执行迭代计算以评估操作数的恒定功率。 形成的中间产品可以在两个路径中进行圆化和归一化，然后压缩并存储以用于下一次迭代。 还可以添加调整常数以增加精确舍入结果的频率。

公开(公告)号：US06175911B1

公开(公告)日：2001-01-16

申请号：US09137583

申请日：1998-08-21

Applicant: Stuart Oberman ,  Stephan G. Meier ,  Manu Gulati

Inventor： Stuart Oberman ,  Stephan G. Meier ,  Manu Gulati

IPC: G06F9302

CPC classification number: G06F7/57 ,  G06F7/535 ,  G06F7/5525 ,  G06F2207/3884

Abstract: A multiplier capable of performing complex iterative calculations such as division and square root concurrently with simple independent multiplication operations is disclosed. The division and square root operations are performed using iterative multiplication operations such as the Newton Raphson iteration and series expansion. These iterative calculations may require a number of passes through the multiplier. Since the multiplier may be pipelined, it may experience a number of idle cycles during the iterative calculations. The multiplier is configured to utilize these idle cycles to perform independent simple multiplication operations. The multiplier may be configured to assert a control signal that is indicative of future idle cycles in the first stages of the multiplier pipeline. The control signal may be used by control logic to dispatch independent simple multiplication operations to the multiplier for execution during the idle clock cycles. The multiplier may also be configured to concurrently execute two independent iterative operations.

Abstract translation: 公开了能够与简单的独立乘法运算同时执行复数迭代计算（例如除法和平方根）的乘法器。 使用诸如牛顿拉夫逊迭代和序列扩展的迭代乘法运算进行除法和平方根运算。 这些迭代计算可能需要通过乘数的多次通过。 由于乘法器可能被流水线化，所以在迭代计算期间可能会遇到多个空闲周期。 乘法器被配置为利用这些空闲周期来执行独立的简单乘法运算。 乘法器可以被配置为断定指示乘法器管线的第一级中的将来的空闲周期的控制信号。 控制信号可以由控制逻辑用于将独立的简单乘法运算发送到乘法器，以在空闲时钟周期期间执行。 乘法器还可以被配置为同时执行两个独立的迭代操作。

公开(公告)号：US6038583A

公开(公告)日：2000-03-14

申请号：US49854

申请日：1998-03-27

Applicant: Stuart Oberman ,  Ming Siu

Inventor： Stuart Oberman ,  Ming Siu

IPC: G06F7/52 ,  G06F7/533 ,  G06F7/544 ,  G06F9/30 ,  G06F9/302 ,  G06F9/318 ,  G06F9/38 ,  G06F17/16 ,  G06F7/38

CPC classification number: G06F7/53 ,  G06F17/16 ,  G06F7/5443 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3017 ,  G06F9/3804 ,  G06F9/3885 ,  G06F2207/3828 ,  G06F7/4991 ,  G06F7/49936 ,  G06F7/49963 ,  G06F7/49994 ,  G06F7/5338

Abstract: A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated based upon each operand's most significant bit and a control signal. The effective signs may then be used to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components. The multiplier may also be configured to sum the products of the vector components to form the vector dot product. The final product may be output in segments so as to require fewer bus lines. The segments may be rounded by adding a rounding constant. Rounding and normalization may be performed in two paths, one assuming an overflow will occur, the other assuming no overflow will occur.

Abstract translation: 公开了能够执行有符号和无符号标量和矢量乘法的乘法器。 乘法器配置为以标量或压缩向量形式接收带符号或无符号乘数和被乘数操作数。 可以基于每个操作数的最高有效位和控制信号来计算乘法器和被乘数操作数的有效符号。 然后根据布斯算法，有效符号可用于创建和选择多个部分乘积。 一旦创建并选择了部分产品，就可以对它们进行求和并输出结果。 结果可能是有符号或无符号的，可能表示向量或标量。 当执行向量乘法时，乘法器可以被配置为产生和选择部分乘积，以便有效地隔离每对向量分量的乘法过程。 乘法器还可以被配置为对矢量分量的乘积求和以形成向量点积。 最终产品可以分段输出，以便需要更少的总线。 可以通过添加舍入常数来对段进行舍入。 可以在两个路径中执行舍入和归一化，一个假设将发生溢出，另一个假设不会发生溢出。