公开(公告)号：US20130105145A1

公开(公告)日：2013-05-02

申请号：US13607391

申请日：2012-09-07

Applicant: Subodh Gupta ,  Simon Gittins

Inventor： Subodh Gupta ,  Simon Gittins

IPC: E21B43/08

CPC classification number: E21B43/08 ,  E21B43/084

Abstract: A wellbore assembly comprises a tubular member adapted to be connected to other tubular members, the tubular member having a side wall defining a hollow interior and an array of openings therethrough to permit material into the interior. A screening element extends about the tubular member over the array of openings to control the material that reaches the array of openings. A stress relieving arrangement associated with the screening element permits relative movement between the screening element and the tubular member to absorb stress build-up within the screening element whether due to mechanical or temperature induced forces that would tend to distortion the screening elements. In a preferred arrangement, the wellbore assembly serves to maintain solids control in production wells while accommodating stresses and strains that occur within the tubular members in those wells.

Abstract translation: 井眼组件包括适于连接到其它管状构件的管状构件，管状构件具有限定中空内部的侧壁和穿过其的开口阵列以允许材料进入内部。 筛选元件围绕管状构件在开口阵列上延伸以控制到达开口阵列的材料。 与筛选元件相关联的应力释放装置允许筛选元件和管状构件之间的相对运动，以吸收筛分元件内的应力积累，无论是由于机械或温度引起的将导致筛选元件变形的力。 在优选的布置中，井筒组件用于在生产井中保持固体控制，同时容纳在这些井中的管状构件内发生的应力和应变。

公开(公告)号：US08104012B1

公开(公告)日：2012-01-24

申请号：US12363721

申请日：2009-01-31

Applicant: Matthew H. Klein ,  Edward S. McGettigan ,  Stephen M. Trimberger ,  James M. Simkins ,  Brian D. Philofsky ,  Subodh Gupta

Inventor： Matthew H. Klein ,  Edward S. McGettigan ,  Stephen M. Trimberger ,  James M. Simkins ,  Brian D. Philofsky ,  Subodh Gupta

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5054 ,  G06F2217/62

Abstract: Dynamic power savings and efficient use of resources are achieved in a programmable logic device (PLD) such as a field programmable gate array (FPGA) or complex programmable logic device (CPLD) by receiving a design netlist specifying a circuit including clock signals, clock buffers, clock enable signals and synchronous elements, examining the design netlist to identify synchronous elements coupled to common clock and clock enable signals, cutting the clock signals to the synchronous elements to form a modified design netlist, inserting gated clock buffers into the modified netlist to output gated clock signals to the synchronous elements, responsive to the clock enable signals, and performing placement and routing on the modified netlist. A system for performing the method on an EDA tool is provided. The methods may be provided as executable instructions stored on a computer readable medium which cause a programmable processor to perform the methods.

Abstract translation: 在诸如现场可编程门阵列（FPGA）或复杂可编程逻辑器件（CPLD）的可编程逻辑器件（PLD）中实现动态功率节省和资源的有效利用，通过接收指定包括时钟信号，时钟缓冲器的电路的设计网表 ，时钟使能信号和同步元件，检查设计网表以识别耦合到公共时钟和时钟使能信号的同步元件，将时钟信号切割到同步元件以形成修改后的设计网表，将门控时钟缓冲器插入修改的网表以输出 门控时钟信号到同步元件，响应于时钟使能信号，并在修改的网表上执行放置和布线。 提供了一种用于在EDA工具上执行该方法的系统。 可以将这些方法提供为存储在计算机可读介质上的可执行指令，其使可编程处理器执行该方法。

公开(公告)号：US07653891B1

公开(公告)日：2010-01-26

申请号：US11710096

申请日：2007-02-23

Applicant: Jason H. Anderson ,  Manoj Chirania ,  Subodh Gupta ,  Philip D. Costello

Inventor： Jason H. Anderson ,  Manoj Chirania ,  Subodh Gupta ,  Philip D. Costello

IPC: H03K17/693

CPC classification number: H03K19/17784 ,  H03K17/005 ,  H03K17/16 ,  H03K19/00346 ,  H03K19/1731

Abstract: A method of reducing power of a circuit is described. The method includes determining at least one unused selection input associated with stages of a multiplexer tree; pulling the at least one unused selection input to a constant value; and assigning predetermined values to unused data inputs of the multiplexer tree associated with the at least one unused selection input.

Abstract translation: 描述了一种降低电路功率的方法。 该方法包括确定与复用器树的阶段相关联的至少一个未使用的选择输入; 将至少一个未使用的选择输入拉至恒定值; 以及将预定值分配给与所述至少一个未使用的选择输入相关联的多路复用器树的未使用的数据输入。