公开(公告)号：US09881118B2

公开(公告)日：2018-01-30

申请号：US14576108

申请日：2014-12-18

Applicant: SYNOPSYS TAIWAN CO., LTD.

Inventor： Hsien-Shih Chiu ,  Kai-Shun Hu

IPC: H01L21/82 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  G06F17/50 ,  H01L23/498

CPC classification number: G06F17/5077 ,  H01L21/4846 ,  H01L23/49811 ,  H01L23/49838 ,  H01L2224/16225

Abstract: A method for routing a circuit device having an array of bump pads includes identifying a routing direction associated with a bump, generating a power strap and a ground strap based on the routing direction, forming a routing channel in accordance with the routing direction, setting a start point and an endpoint in the routing channel, and connecting the start point and the endpoint using a wire within the routing channel. The method further includes placing the start point to a power or ground strap in response to a target power/ground ratio.

公开(公告)号：US09852251B2

公开(公告)日：2017-12-26

申请号：US14203300

申请日：2014-03-10

Applicant: Synopsys, Inc. ,  Synopsys Taiwan Co., Ltd.

Inventor： Hsiao-Tzu Lu ,  Duncan Robert McDonald ,  Chih-Wei Yuan ,  Wen-Lung Kang

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5068

Abstract: A system, apparatus and computer-implemented method for manipulating a parameterized cell device into a custom layout design. The method begins by receiving at least one parameterized cell representing a physical circuit from, for example, a database or configuration file. The parameterized cell has a plurality of configurable attributes. The method continues by adjusting one of the configurable attributes of the parameterized cell according to a capability associated with the one attribute. The attributes may include one or more of a parameter mapping capability, a port mapping capability, an abutment capability, a directional extension capability, a channel width capability, and a boundary layer capability. The method then calculates a new configuration for the parameterized cell based upon the adjustment, and applies the new configuration for the parameterized cell to a layout of the represented physical circuit.

公开(公告)号：US20170316143A1

公开(公告)日：2017-11-02

申请号：US15654363

申请日：2017-07-19

Applicant: Synopsys Taiwan Co., Ltd.

Inventor： Chien-Hung Lu ,  Chun-Chen Chi ,  Tung-Chieh Chen ,  Kai-Chih Chi

IPC: G06F17/50

Abstract: A computer implemented method of routing a net of an electronic circuit is disclosed. The net connects a plurality of pins of the electronic circuit. The method includes selecting, using one or more computer systems, first and second main spine routing tracks for respective first and second groups of pins of the net. The method also includes generating, using one or more computer systems, a first main spine wire on the selected first main spine routing track and a second main spine wire on the selected second main spine routing track. A router configured to perform the method is also disclosed.

公开(公告)号：US09384313B2

公开(公告)日：2016-07-05

申请号：US14253784

申请日：2014-04-15

Applicant: Synopsys, Inc. ,  Synopsys Taiwan Co., Ltd.

Inventor： Hung Chun Chiu ,  Meng-Chyi Lin ,  Kuen-Yang Tsai ,  Sweyyan Shei ,  Hwa Mao ,  Yingtsai Chang

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F2217/14

Abstract: User's register transfer level (RTL) design is analyzed and instrumented so that signals of interest are preserved and can be located in the netlist after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the netlist to ensure that signal values can be accessed at runtime. After that, a place and route (P&R) process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations is field programmable gate array (FPGA) devices. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names.

Abstract translation: 用户的寄存器传输级别（RTL）设计进行分析和检测，以使感兴趣的信号得以保留，并且可以在合成后位于网表中。 然后，执行用户的RTL合成和设计分区的原始流程。 分析输出以定位感兴趣的信号。 锁存器有选择地插入到网表中，以确保在运行时可以访问信号值。 之后，执行位置和路由（P＆R）处理，分析输出以将信号名称与寄存器（触发器和锁存器）或存储器块相关联，位置是现场可编程门阵列（FPGA）器件。 建立并保存关联数据库以供运行时使用。 在运行期间，可以在工作站上提供软件组件，供用户查询与RTL分层信号名称对应的信号值。

公开(公告)号：US20160110484A1

公开(公告)日：2016-04-21

申请号：US14791216

申请日：2015-07-02

Applicant: Synopsys Taiwan Co., Ltd. ,  Synopsys, Inc.

Inventor： Yung Chuan CHEN ,  I-Liang LIN ,  Li-Chi CHANG ,  Bindesh PATEL

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F11/3672

Abstract: Methods and apparatus for recording and visualizing transactions of a test bench simulation are disclosed. Transaction-specific data generated from a test bench simulation may be displayed in a sequence diagram view to provide a view of the transactions arranged sequentially in time.

Abstract translation: 公开了用于记录和可视化测试台模拟的交易的方法和装置。 可以在序列图视图中显示从测试台仿真生成的特定于事务的数据，以提供按时间顺序排列的事务的视图。

公开(公告)号：US20150143310A1

公开(公告)日：2015-05-21

申请号：US14541555

申请日：2014-11-14

Applicant: Synopsys Taiwan Co., Ltd.

Inventor： Wei-Cheng Chen ,  Jen-Feng Huang

IPC: G06F17/50

CPC classification number: G06F17/5045

Abstract: In one or more embodiments, a caching apparatus includes functionality to persist evaluation results associated with pcells in a design across sessions of an EDA application as well as across design libraries. The caching apparatus may create and maintain a mirror cache in a design library with only subMasters referenced by the design library. The contents of a central cache file or a mirror cache in the design library are examined for an evaluation result. If the evaluation result is not found in the central cache file, the evaluation result may be retrieved from the mirror cache if present.

Abstract translation: 在一个或多个实施例中，高速缓存设备包括在EDA应用程序的跨会话以及跨设计库中的设计中持续与pcell相关联的评估结果的功能。 缓存设备可以在设计库中创建和维护镜像缓存，只有设计库引用的subMasters。 检查设计库中的中央缓存文件或镜像缓存的内容以进行评估结果。 如果在中央缓存文件中没有找到评估结果，则可以从镜像缓存中检索评估结果（如果存在）。

公开(公告)号：US20150100938A1

公开(公告)日：2015-04-09

申请号：US14508205

申请日：2014-10-07

Applicant: Synopsys Taiwan Co., Ltd.

Inventor： Chien-Hung Lu ,  Chun-Cheng CHI ,  Tung-Chieh CHEN

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F2217/08 ,  G06F2217/82

Abstract: A computer implemented method of routing a net of an electronic circuit is disclosed. The net connects a plurality of pins of the electronic circuit. The method includes selecting, using one or more computer systems, first and second main spine routing tracks for respective first and second groups of pins of the net. The method also includes generating, using one or more computer systems, a first main spine wire on the selected first main spine routing track and a second main spine wire on the selected second main spine routing track. A router configured to perform the method is also disclosed.

Abstract translation: 公开了一种用于布置电子电路网的计算机实现方法。 网络连接电子电路的多个引脚。 该方法包括：使用一个或多个计算机系统选择网的相应的第一和第二组引脚的第一和第二主脊线路由轨道。 该方法还包括使用一个或多个计算机系统在所选择的第一主脊柱路径轨道上产生第一主脊线，以及在所选择的第二主脊线路径轨道上生成第二主脊线。 还公开了配置为执行该方法的路由器。

公开(公告)号：US08839179B2

公开(公告)日：2014-09-16

申请号：US13856004

申请日：2013-04-03

Applicant: Synopsys Taiwan Co., Ltd.

Inventor： Yingtsai Chang ,  Sweyyan Shei ,  Hung-Chun Chiu ,  Meng-Chyi Lin ,  Hwa Mao ,  Ming Yang Wang ,  Yuchin Hsu

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5027

Abstract: A test system for testing prototype designs includes a host workstation, multiple interface devices, and multiple prototype boards. The prototype boards include programmable devices which implement one or more partitions of a user design and an associated verification modules. The verification modules probe signals of the partitions and transmit the probed signals to the interface devices. The verification modules can also transmit output signals generated by one or more partitions on the prototype boards to the host workstation via the interface devices, and transmit input signals, which are received from the host workstation via the interface devices, to one or more partitions on the prototype boards.

Abstract translation: 用于测试原型设计的测试系统包括主机工作站，多个接口设备和多个原型板。 原型板包括实现用户设计的一个或多个分区和相关联的验证模块的可编程设备。 验证模块探测分区的信号，并将探测信号发送到接口设备。 验证模块还可以通过接口设备将原型板上的一个或多个分区产生的输出信号发送到主机工作站，并且通过接口设备将从主机工作站接收的输入信号发送到一个或多个分区上 原型板。

公开(公告)号：US20140165023A1

公开(公告)日：2014-06-12

申请号：US13954783

申请日：2013-07-30

Applicant: Synopsys Taiwan Co., Ltd. ,  Synopsys, Inc.

Inventor： Chia-Ling Ho ,  Jian-Cheng Lin ,  Jencheng Wang

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F11/362 ,  G06F11/3636 ,  G06F17/5009

Abstract: A computer-implemented method to debug testbench code of a testbench associated with a circuit design by recording a trace of call frames along with activities of the circuit design. By correlating and displaying the recorded trace of call frames, the method enables users to easily trace as execution history of subroutines executed by the testbench thereby to debug the testbench code. In addition, users can trace source code of the testbench code by using the recorded trace of call frames. Furthermore, users can debug the testbench code utilizing a virtual simulation, which is done by post-processing records of the virtual simulation stored in a database.

Abstract translation: 一种计算机实现的方法，用于通过记录呼叫帧的跟踪以及电路设计的活动来调试与电路设计相关联的测试台的测试台代码。 通过关联和显示记录的调用帧轨迹，该方法使用户能够轻松跟踪由测试台执行的子程序的执行历史，从而调试测试平台代码。 此外，用户可以通过使用记录的调用帧跟踪来跟踪测试平台代码的源代码。 此外，用户可以使用虚拟仿真来调试测试平台代码，虚拟仿真是通过后处理存储在数据库中的虚拟仿真的记录完成的。

公开(公告)号：US20140143747A1

公开(公告)日：2014-05-22

申请号：US14086158

申请日：2013-11-21

Applicant: Synopsys Taiwan Co., LTD.

Inventor： Hsin-Po Wang ,  Song Yuan ,  Hung-Shih Wang

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A computer-implemented method for routing at least one conductor includes generating the at least one conductor within a bounded region on a planar surface in accordance with a template, and placing at least one slit in the conductor when the conductor overlaps a specified region of the bounded region in accordance with a specified pattern.

Abstract translation: 用于布线至少一个导体的计算机实现的方法包括根据模板在平坦表面上的有界区域内生成至少一个导体，并且当导体与导体重叠在一个特定的区域时，在导体中放置至少一个狭缝 有界区域按照指定的模式。