公开(公告)号：US06335889B1

公开(公告)日：2002-01-01

申请号：US09688797

申请日：2000-10-17

申请人： Tadashi Onodera

发明人： Tadashi Onodera

IPC分类号： G11C700

CPC分类号： G11C7/1012 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1042 ,  G11C7/18 ,  G11C11/4096 ,  G11C11/4097

摘要： A semiconductor memory device is disclosed that is capable of outputting in the fastest possible time the first of serial data that are read in bursts, despite the increase in capacity of a memory cell array. In this semiconductor memory device, for a single address access, a plurality of bits of serial data are read in a burst from a memory sub-array that is made up by memory cell arrays 11Uo and 11Ue or memory cell arrays 11Le and 11Lo. In order that the serial data that are read first are the data of bit 0 regardless of the operation mode of the semiconductor memory device, each individual memory sub-array is divided between portions for even data and portions for odd data and the even memory cell arrays 11Ue and 11Le in which the data of bit 0 are stored are arranged closer to the data amplifier than the odd memory cell arrays 11Uo and 11Lo. The maximum length of I/O lines that are used in reading even data is therefore about half that of the maximum length of I/O lines that are used in reading odd data.

摘要翻译： 公开了一种半导体存储器件，尽管存储器单元阵列的容量增加，但能够以尽可能快的时间输出以脉冲串方式读取的第一串行数据。 在该半导体存储器件中，对于单个地址存取，从由存储单元阵列11Uo和11Ue或存储单元阵列11Le和11Lo组成的存储器子阵列以脉冲串形式读取多个串行数据位。 为了首先读取的串行数据是位0的数据，而与半导体存储器件的操作模式无关，每个单独的存储器子阵列被划分用于偶数据的部分和用于奇数数据的部分和偶数存储单元 存储位0的数据的阵列11Ue和11Le比奇数存储单元阵列11Uo和11Lo更靠近数据放大器布置。 因此，用于读取偶数据的I / O线的最大长度约为读取奇数数据时使用的I / O线的最大长度的一半。

公开(公告)号：US6084391A

公开(公告)日：2000-07-04

申请号：US325733

申请日：1999-06-04

申请人： Tadashi Onodera

发明人： Tadashi Onodera

IPC分类号： G05F3/02 ,  G05F3/24 ,  G05F3/26 ,  G05F3/16

CPC分类号： G05F3/242 ,  G05F3/262

摘要： In a bandgap reference voltage generating circuit having first, second and third unitary circuits connected in parallel between a power supply voltage and a ground, there is added a fourth unitary circuit including an n-channel FET turned on in response to a bias voltage applied to a gate of the n-channel FET. The second unitary circuit is connected to the fourth unitary circuit through a capacitor having one end connected to a drain of the n-channel FET. When the bias voltage is applied to turn on the n-channel FET of the fourth unitary circuit, since the potential of the one end of the capacitor is dropped, a gate potential of n-channel FETs included in the first and second unitary circuits and operating in a weak inversion condition quickly becomes definite, so that a reference voltage can be generated quickly.

摘要翻译： 在具有在电源电压和地之间并联连接的第一，第二和第三整体电路的带隙参考电压产生电路中，添加了第四单元电路，其包括响应于施加到 n沟道FET的栅极。 第二单元电路通过电容器连接到第四单元电路，电容器的一端连接到n沟道FET的漏极。 当施加偏置电压以接通第四单元电路的n沟道FET时，由于电容器一端的电位下降，所以包含在第一和第二单元电路中的n沟道FET的栅极电位和 在弱反转条件下运行变得明确，从而可以快速产生参考电压。