公开(公告)号：US5594649A

公开(公告)日：1997-01-14

申请号：US357883

申请日：1994-12-19

Applicant: Thomas D. Cook ,  Manuel R. Fairchild ,  Kenneth D. Mowery ,  Jeffrey R. Scott

Inventor： Thomas D. Cook ,  Manuel R. Fairchild ,  Kenneth D. Mowery ,  Jeffrey R. Scott

IPC: G01L23/22

CPC classification number: G01L23/225

Abstract: An engine knock control system that can be digitally reconfigured to operate in different knock signal processing modes. The system includes a knock detection circuit that processes an incoming knock signal produced by a vibration or pressure sensor on the engine. The circuit includes a plurality of circuit devices that are capable of being interconnected in different circuit topology configurations to thereby process the knock signal in a selected one of a plurality of different modes. The circuit includes hardware and software for forming a selected interconnection configuration of the circuit devices in response to a coded data signal input to the circuit.

Abstract translation: 一种引擎爆震控制系统，可以数字重新配置，以不同的爆震信号处理模式运行。 该系统包括爆震检测电路，其处理由发动机上的振动或压力传感器产生的输入爆震信号。 该电路包括能够以不同的电路拓扑配置互连的多个电路装置，从而以多种不同模式中选择的一种来处理爆震信号。 电路包括硬件和软件，用于响应于输入到电路的编码数据信号形成电路装置的选定互连配置。

公开(公告)号：US08310877B2

公开(公告)日：2012-11-13

申请号：US12985724

申请日：2011-01-06

Applicant: Jeffrey C. Cunningham ,  Thomas D. Cook ,  Stephen F. McGinty ,  Ronald J. Syzdek

Inventor： Jeffrey C. Cunningham ,  Thomas D. Cook ,  Stephen F. McGinty ,  Ronald J. Syzdek

IPC: G11C16/04

CPC classification number: G11C16/28 ,  G11C11/14 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/3418

Abstract: A method and memory are provided for determining a read reference level for a plurality of non-volatile memory cells. The method includes: performing a program operation of the plurality of non-volatile memory cells; determining a program level of a least programmed memory cell of the plurality of memory cells; performing an erase operation of the plurality of non-volatile memory cells; determining an erase level of a least erased memory cell of the plurality of memory cells; determining an operating window between the program level and the erase level; and setting the read reference level to be a predetermined offset from the erase level if the operating window is determined to compare favorably to a predetermined value. The memory includes registers for storing the program level and the erase level.

Abstract translation: 提供了一种用于确定多个非易失性存储器单元的读取参考电平的方法和存储器。 该方法包括：执行多个非易失性存储单元的编程操作; 确定所述多个存储器单元中的最小程序存储单元的程序级; 执行所述多个非易失性存储单元的擦除操作; 确定所述多个存储器单元中最少擦除的存储单元的擦除电平; 确定程序级和擦除级之间的操作窗口; 并且如果确定操作窗口与预定值相比较，则将读取参考电平设置为与擦除电平的预定偏移。 存储器包括用于存储程序电平和擦除电平的寄存器。

公开(公告)号：US20110316592A1

公开(公告)日：2011-12-29

申请号：US12823487

申请日：2010-06-25

Applicant: Thomas D. Cook ,  Jeffrey C. Cunningham ,  Karthik Ramanan

Inventor： Thomas D. Cook ,  Jeffrey C. Cunningham ,  Karthik Ramanan

IPC: H03L7/00

CPC classification number: G06F1/3206 ,  G06F1/3275 ,  G11C5/148 ,  G11C16/30 ,  Y02D10/14

Abstract: A target circuit of an electronic device is placed in a suspended mode by disconnecting the target circuit from one or more voltage sources. A refresh controller periodically initiates a refresh operation during the suspended mode by temporarily reconnecting the target circuit to the one or more voltage sources for a duration sufficient to recharge capacitances of the target circuit. The refresh controller terminates the refresh operation by disconnecting the target circuit from the one or more voltage sources, thereby continuing the suspended mode of the electronic device. The refresh controller can employ a Very Low Frequency Oscillator (VLFO) to time the frequency of refresh operations. The VLFO manages the refresh initialization timing based on the voltage across a capacitor that is selectively charged or discharged so as to implement the refresh operation. The refresh controller further can employ a counter to time the duration of the refresh operation.

Abstract translation: 通过将目标电路与一个或多个电压源断开而将电子设备的目标电路置于暂停模式。 刷新控制器在暂停模式期间周期性地启动刷新操作，通过将目标电路临时重新连接到一个或多个电压源，持续时间足以再充电目标电路的电容。 刷新控制器通过将目标电路与一个或多个电压源断开而终止刷新操作，由此继续电子设备的挂起模式。 刷新控制器可以使用超低频振荡器（VLFO）来计时刷新操作的频率。 VLFO基于选择性地充电或放电的电容器上的电压来管理刷新初始化时序，以便实现刷新操作。 刷新控制器还可以使用计数器来刷新操作的持续时间。

公开(公告)号：US08040700B2

公开(公告)日：2011-10-18

申请号：US12619303

申请日：2009-11-16

Applicant: Thomas D. Cook ,  Jeffrey C. Cunningham ,  Karthik Ramanan

Inventor： Thomas D. Cook ,  Jeffrey C. Cunningham ,  Karthik Ramanan

IPC: H02M3/18

CPC classification number: H02M3/07

Abstract: A charge pump has circuitry and implements a method for monitoring a synchronous load by using a first voltage threshold below a target output voltage and a second voltage threshold above a target output voltage. An output terminal is coupled to the load. Charge is demanded by clocking the load. When the target output voltage passes below the first voltage threshold, a first value representing a present size of a charging capacitance is stored as a stored first value, and a second stored value representing a needed changed size of the charging capacitance is used. The present size of the charging capacitance is changed in response to the passing of the target output voltage below the first voltage threshold. When demand for charge from the load is reduced, a present value is saved and a prior value is restored to change the size of the charging capacitance.

Abstract translation: 电荷泵具有电路并且实现了通过使用低于目标输出电压的第一电压阈值和高于目标输出电压的第二电压阈值来监视同步负载的方法。 输出端子耦合到负载。 通过计时负载需要充电。 当目标输出电压通过低于第一电压阈值时，表示充电电容的当前尺寸的第一值被存储为存储的第一值，并且使用表示充电电容所需改变的尺寸的第二存储值。 响应于目标输出电压的通过低于第一电压阈值，充电电容的当前尺寸被改变。 当减少对负载的充电需求时，保存当前值并恢复先前值以改变充电电容的尺寸。

公开(公告)号：US07948301B2

公开(公告)日：2011-05-24

申请号：US12549499

申请日：2009-08-28

Applicant: Thomas D. Cook ,  Jeffrey C. Cunningham ,  Karthik Ramanan

Inventor： Thomas D. Cook ,  Jeffrey C. Cunningham ,  Karthik Ramanan

IPC: G05F1/10

CPC classification number: H02M3/07 ,  H02M2003/077

Abstract: A charge pump charges a first capacitor to a predetermined input voltage using a first switch. The first switch is coupled to a first terminal of the first capacitor for coupling the first terminal to an input terminal that receives the predetermined input voltage. A second switch couples a second terminal of the first capacitor to a reference voltage terminal. Charge is sequentially transferred from the first capacitor to an output capacitance by using the first switch. A portion of charge is sequentially removed from the output capacitance to the input terminal using a third switch and a second capacitor. Configuration logic provides control signals to make one or more of a plurality of charge transfer capacitors switch the same as said first capacitor switches.

Abstract translation: 电荷泵使用第一开关将第一电容器充电至预定的输入电压。 第一开关耦合到第一电容器的第一端子，用于将第一端子耦合到接收预定输入电压的输入端子。 第二开关将第一电容器的第二端子耦合到参考电压端子。 通过使用第一开关将充电从第一电容器依次传送到输出电容。 使用第三开关和第二电容器将一部分电荷从输出电容顺序地移除到输入端。 配置逻辑提供控制信号以使得多个电荷转移电容器中的一个或多个与所述第一电容器开关相同。

公开(公告)号：US20110115549A1

公开(公告)日：2011-05-19

申请号：US12619303

申请日：2009-11-16

Applicant: Thomas D. Cook ,  Jeffrey C. Cunningham ,  Karthik Ramanan

Inventor： Thomas D. Cook ,  Jeffrey C. Cunningham ,  Karthik Ramanan

IPC: G05F1/10

CPC classification number: H02M3/07

Abstract: A charge pump has circuitry and implements a method for monitoring a synchronous load by using a first voltage threshold below a target output voltage and a second voltage threshold above a target output voltage. An output terminal is coupled to the load. Charge is demanded by clocking the load. When the target output voltage passes below the first voltage threshold, a first value representing a present size of a charging capacitance is stored as a stored first value, and a second stored value representing a needed changed size of the charging capacitance is used. The present size of the charging capacitance is changed in response to the passing of the target output voltage below the first voltage threshold. When demand for charge from the load is reduced, a present value is saved and a prior value is restored to change the size of the charging capacitance.

Abstract translation: 电荷泵具有电路并且实现了通过使用低于目标输出电压的第一电压阈值和高于目标输出电压的第二电压阈值来监视同步负载的方法。 输出端子耦合到负载。 通过计时负载需要充电。 当目标输出电压通过低于第一电压阈值时，表示充电电容的当前尺寸的第一值被存储为存储的第一值，并且使用表示充电电容所需改变的尺寸的第二存储值。 响应于目标输出电压的通过低于第一电压阈值，充电电容的当前尺寸被改变。 当减少对负载的充电需求时，保存当前值并恢复先前值以改变充电电容的尺寸。

公开(公告)号：US07560970B2

公开(公告)日：2009-07-14

申请号：US11835552

申请日：2007-08-08

Applicant: Thomas D. Cook ,  Tahmina Akhter ,  Jeffrey C. Cunningham

Inventor： Thomas D. Cook ,  Tahmina Akhter ,  Jeffrey C. Cunningham

IPC: H03L5/00

CPC classification number: H03K3/35613

Abstract: A level converter comprises first and second latches, and first through fourth transistors. The first latch has first and second power supply terminals, and first and second nodes. The second latch has third and fourth power supply terminals, and third and fourth nodes. The first transistor has a first current electrode coupled to the first node, a control electrode coupled to receive a first bias voltage, and a second current electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to the third node, and a control electrode coupled to receive a second bias voltage. The third transistor has a first current electrode coupled to the second node, a control electrode coupled to receive the first bias voltage, and a second current electrode. The fourth transistor has a first current electrode coupled to the second current electrode of the third transistor, a control electrode coupled to receive the second bias voltage, and a second current electrode coupled to the fourth node.

Abstract translation: 电平转换器包括第一和第二锁存器以及第一至第四晶体管。 第一锁存器具有第一和第二电源端子以及第一和第二节点。 第二锁存器具有第三和第四电源端子，以及第三和第四节点。 第一晶体管具有耦合到第一节点的第一电流电极，耦合以接收第一偏置电压的控制电极和第二电流电极。 第二晶体管具有耦合到第一晶体管的第二电流电极的第一电流电极，耦合到第三节点的第二电流电极和耦合以接收第二偏置电压的控制电极。 第三晶体管具有耦合到第二节点的第一电流电极，耦合以接收第一偏置电压的控制电极和第二电流电极。 第四晶体管具有耦合到第三晶体管的第二电流电极的第一电流电极，耦合以接收第二偏置电压的控制电极和耦合到第四节点的第二电流电极。

公开(公告)号：US4749955A

公开(公告)日：1988-06-07

申请号：US946780

申请日：1986-12-29

Applicant: Thomas D. Cook

Inventor： Thomas D. Cook

IPC: H03F3/45

CPC classification number: H03F3/45179 ,  H03F2203/45364 ,  H03F2203/45394 ,  H03F2203/45664 ,  H03F2203/45674

Abstract: A low voltage comparator circuit including a differential amplifier circuit, a double-ended to single-ended conversion circuit, and an inverting amplifier circuit is disclosed. The differential amplifier circuit consists of two identical current paths, each having one upper and one lower MOSFET device connected together in series between supply voltage and ground. Each of two input voltages is applied directly to the gate of the upper MOSFET device in one current path and is also coupled, after being inverted, to the gate of the lower MOSFET device in the opposite current path, respectively.

Abstract translation: 公开了一种包括差分放大器电路，双端到单端转换电路和反相放大器电路的低电压比较器电路。 差分放大器电路由两个相同的电流路径组成，每个电路具有一个在电源电压和地之间串联连接在一起的上MOSFET和下MOSFET组件。 两个输入电压中的每一个在一个电流路径中直接施加到上MOSFET器件的栅极，并且在反相之后分别耦合到相反电流路径中的下MOSFET器件的栅极。

公开(公告)号：US20120176844A1

公开(公告)日：2012-07-12

申请号：US12985724

申请日：2011-01-06

Applicant: Jeffrey C. Cunningham ,  Thomas D. Cook ,  Stephen F. McGinty ,  Ronald J. Syzdek

Inventor： Jeffrey C. Cunningham ,  Thomas D. Cook ,  Stephen F. McGinty ,  Ronald J. Syzdek

IPC: G11C16/06

CPC classification number: G11C16/28 ,  G11C11/14 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/3418

Abstract: A method and memory are provided for determining a read reference level for a plurality of non-volatile memory cells. The method includes: performing a program operation of the plurality of non-volatile memory cells; determining a program level of a least programmed memory cell of the plurality of memory cells; performing an erase operation of the plurality of non-volatile memory cells; determining an erase level of a least erased memory cell of the plurality of memory cells; determining an operating window between the program level and the erase level; and setting the read reference level to be a predetermined offset from the erase level if the operating window is determined to compare favorably to a predetermined value. The memory includes registers for storing the program level and the erase level.

Abstract translation: 提供了一种用于确定多个非易失性存储器单元的读取参考电平的方法和存储器。 该方法包括：执行多个非易失性存储单元的编程操作; 确定所述多个存储器单元中的最小程序存储单元的程序级; 执行所述多个非易失性存储单元的擦除操作; 确定所述多个存储器单元中最少擦除的存储单元的擦除电平; 确定程序级和擦除级之间的操作窗口; 并且如果确定操作窗口与预定值相比较，则将读取参考电平设置为与擦除电平的预定偏移。 存储器包括用于存储程序电平和擦除电平的寄存器。

公开(公告)号：US07889523B2

公开(公告)日：2011-02-15

申请号：US11870259

申请日：2007-10-10

Applicant: Thomas D. Cook ,  Tahmina Akhter ,  Jeffrey C. Cunningham

Inventor： Thomas D. Cook ,  Tahmina Akhter ,  Jeffrey C. Cunningham

IPC: H02M3/28 ,  H02M7/00

CPC classification number: H02M3/07

Abstract: A charge-based voltage multiplier device comprising a charge-pump circuit and a charge-pump controller is provided. The charge-pump circuit is configured to multiply an input voltage signal (Vin) into an output voltage signal (Vout), the charge-pump circuit includes a plurality of charge-pump stages, wherein at least one of the charge-pump stages includes a weighted capacitor array of pump cells. The charge-pump controller is configured to provide a pump cell select to selectively control the weighted capacitor array of pump cells of the at least one of the charge-pump stages of the charge-pump circuit.

Abstract translation: 提供了一种基于电荷的电压倍增器装置，其包括电荷泵电路和电荷泵控制器。 电荷泵电路被配置为将输入电压信号（Vin）乘以输出电压信号（Vout），电荷泵电路包括多个电荷泵级，其中至少一个电荷泵级包括 泵电池的加权电容器阵列。 电荷泵控制器被配置为提供泵电池选择以选择性地控制电荷泵电路的至少一个电荷泵级的泵电池的加权电容器阵列。