公开(公告)号：US6083802A

公开(公告)日：2000-07-04

申请号：US223840

申请日：1998-12-31

申请人： Wen Ying Wen ,  Shing Shing Chiang

发明人： Wen Ying Wen ,  Shing Shing Chiang

IPC分类号： H01L21/02 ,  H01L27/06 ,  H01L27/08 ,  H01L21/20

CPC分类号： H01L28/10 ,  H01L27/0617 ,  H01L27/08

摘要： A method for forming an inductor in a semiconductor substrate having a trench therein including the steps of forming a first metal portion in the trench, providing a flowable dielectric material in the trench, depositing a layer of dielectric material over the layer of first metal portion and flowable dielectric material, forming a plug in the layer of dielectric material wherein the plug is in electrical contact with the first metal portion, and forming a second metal portion over the layer of dielectric material wherein the second metal portion is in electrical contact with the plug.

摘要翻译： 一种在其中具有沟槽的半导体衬底中形成电感器的方法，包括在沟槽中形成第一金属部分的步骤，在沟槽中提供可流动的电介质材料，在第一金属部分的层上沉积介电材料层， 在所述电介质材料层中形成插塞，其中所述插塞与所述第一金属部分电接触，以及在所述电介质材料层上形成第二金属部分，其中所述第二金属部分与所述插头电接触 。

公开(公告)号：US5651859A

公开(公告)日：1997-07-29

申请号：US550855

申请日：1995-10-31

申请人： Tung-Yi Chan ,  Wen-Ying Wen

发明人： Tung-Yi Chan ,  Wen-Ying Wen

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L21/00

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method for manufacturing a semiconductor memory cell with a floating gate having a predetermined length includes the steps of: growing a thin oxide layer over a substrate; depositing a polysilicon layer over the thin oxide layer; depositing a silicon nitride layer over the polysilicon layer; masking and etching the nitride layer down to the polysilicon layer so as to form an oxide receiving groove in the nitride layer, the groove being parallel to a longitudinal axis of the floating gate to be formed and being longer than the predetermined width of the floating gate to be formed, and the width of the receiving groove in latitudal axis is equal to the predetermined length of the floating gate, the receiving groove overlapping a floating gate region to be defined on the polysilicon layer; growing a polysilicon oxide layer in the receiving groove; removing the nitride layer; providing a mask which is transverse to the polysilicon oxide layer and which has a width equal to the predetermined length of the floating gate to be formed, the mask covering a portion of the polysilicon oxide layer which is directly above the floating gate region; etching remaining portion of the polysilicon oxide layer not covered by the mask; removing the mask; and etching the polysilicon layer with the portion of the polysilicon oxide layer serving as a mask so as to form the floating gate.

摘要翻译： 制造具有预定长度的浮动栅极的半导体存储单元的方法包括以下步骤：在衬底上生长薄氧化物层; 在所述薄氧化物层上沉积多晶硅层; 在所述多晶硅层上沉积氮化硅层; 掩蔽和蚀刻氮化物层到多晶硅层，以在氮化物层中形成氧化物接收槽，该沟槽平行于待形成的浮动栅极的纵向轴线并且比浮动栅极的预定宽度长 并且宽度方向上的接收槽的宽度等于浮栅的预定长度，接收槽与多晶硅层上限定的浮栅区重叠; 在接收槽中生长多晶硅氧化物层; 去除氮化物层; 提供与多晶硅氧化物层横向并且具有等于要形成的浮置栅极的预定长度的宽度的掩模，所述掩模覆盖位于浮动栅极区域正上方的多晶硅氧化物层的一部分; 蚀刻未被掩模覆盖的多晶硅氧化物层的剩余部分; 去除面膜; 并且用多晶硅氧化物层的部分作为掩模蚀刻多晶硅层，以形成浮置栅极。

公开(公告)号：US06727145B1

公开(公告)日：2004-04-27

申请号：US10327972

申请日：2002-12-26

申请人： Wen Ying Wen

发明人： Wen Ying Wen

IPC分类号： H01L21336

CPC分类号： H01L27/11226 ,  G11C16/10 ,  G11C2216/26 ,  H01L27/112

摘要： The present invention generally relates to a method for fabricating a post-process one-time programmable (OTP) read only memory cell (ROM cell). The OTP ROM cell has two oxide layers positioned on a semiconductor substrate and a plurality of semiconductor-implanted regions are implanted in the semiconductor substrate. Oxide layers are respectively to those semiconductor-implanted regions of the semiconductor substrate and having a window-type isolating channel region for each. Finally, a polysilicon layer is positioned on the thicker oxide layer as a gate electrode region of the OTP ROM cell. Hence, the polysilicon layer can be applied a voltage to penetrate the thinker oxide layer of the window-type isolating channel region to form a P-N junction between the semiconductor-implanted regions and the polysilicon layer and then the ROM cell is programmed.

摘要翻译： 本发明一般涉及用于制造后处理一次可编程（OTP）只读存储单元（ROM单元）的方法。 OTP ROM单元具有位于半导体衬底上的两个氧化物层，并且多个半导体注入区被注入到半导体衬底中。 氧化物层分别与半导体衬底的那些半导体注入区并且具有各自的窗型绝缘沟道区。 最后，将多晶硅层定位在较厚的氧化物层上作为OTP ROM单元的栅电极区域。 因此，多晶硅层可以施加电压以穿透窗型隔离沟道区的思维者氧化物层，以在半导体注入区域和多晶硅层之间形成P-N结，然后对ROM单元进行编程。

公开(公告)号：US06469362B2

公开(公告)日：2002-10-22

申请号：US09505148

申请日：2000-02-15

申请人： Shyh-Chyi Wong ,  Wen-Ying Wen

发明人： Shyh-Chyi Wong ,  Wen-Ying Wen

IPC分类号： H01L2900

CPC分类号： H01L27/0623 ,  H01L21/8249

摘要： An integrated circuit device includes a semiconductor substrate, an NMOS, a PMOS contiguous with the NMOS, and a composite pnp bipolar junction transistor contiguous with the NMOS. The composite pnp bipolar junction transistor includes a lateral npn bipolar junction transistor having a first current gain, and a lateral pnp bipolar junction transistor having a second current gain, wherein the current gain of the composite pnp bipolar junction transistor equals the first current gain multiplied by the second current gain.

摘要翻译： 集成电路器件包括半导体衬底，NMOS，与NMOS连接的PMOS以及与NMOS相邻的复合pnp双极结晶体管。 复合pnp双极结晶体管包括具有第一电流增益的横向npn双极结型晶体管和具有第二电流增益的横向pnp双极结型晶体管，其中复合pnp双极结型晶体管的电流增益等于第一电流增益乘以 第二个电流增益。

公开(公告)号：US5918121A

公开(公告)日：1999-06-29

申请号：US113019

申请日：1998-07-09

申请人： Wen-Ying Wen ,  Chih-Ming Chen

发明人： Wen-Ying Wen ,  Chih-Ming Chen

IPC分类号： H01L21/02 ,  H01L27/08 ,  H01L29/86 ,  H01L29/72 ,  H01L21/76

CPC分类号： H01L28/10 ,  H01L27/08 ,  H01L29/86

摘要： A method for making planar silicon-based inductor structure with improved Q is disclosed. This method includes the steps of: (a) providing a lightly-doped P-type substrate as a starting wafer; (b) forming a preliminary oxide layer on the lightly-doped P-type substrate; (c) forming a first oxide layer from the preliminary oxide layer enclosing a predetermined epitaxial area; (d) depositing an epitaxial layer in the epitaxial area using intrinsic doping; (e) forming a second oxide layer which covers both the epitaxial layer and the first oxide layer, and is merged with the first oxide layer to thus form a contiguous inter-connected inductor oxide layer; (f) forming a metal line according to a planar inductor pattern so as to form a silicon-based inductor structure. The epitaxial layer has a resistivity of at least 2 K ohm-cm. The planar silicon-based inductor improves the Q value by reducing or stopping current losses into the substrate.

摘要翻译： 公开了一种制造具有改进Q的平面硅基电感器结构的方法。 该方法包括以下步骤：（a）提供轻掺杂的P型衬底作为起始晶片; （b）在轻掺杂的P型衬底上形成预氧化物层; （c）从包围预定外延区域的预备氧化物层形成第一氧化物层; （d）使用本征掺杂在外延区中沉积外延层; （e）形成覆盖所述外延层和所述第一氧化物层的第二氧化物层，并且与所述第一氧化物层合并从而形成连续的相互连接的电感器氧化物层; （f）根据平面电感器图案形成金属线以形成硅基电感器结构。 外延层具有至少2KΩ·cm的电阻率。 平面硅基电感器通过减少或阻止电流损耗进入衬底来提高Q值。