公开(公告)号：US5999449A

公开(公告)日：1999-12-07

申请号：US239072

申请日：1999-01-27

Applicant: Sunil D. Mehta ,  Xiao-Yu Li

Inventor： Sunil D. Mehta ,  Xiao-Yu Li

IPC: G11C16/04 ,  G11C11/34

CPC classification number: G11C16/0441

Abstract: A two transistor EEPROM cell is described that is programmed and erased by electron tunneling across a tunneling channel in a P-well. The EEPROM cell has two transistors formed in a semiconductor substrate. The two transistors are a tunneling transistor (NMOS) and a read transistor (NMOS). Electron tunneling occurs to program and erase the EEPROM cell through a tunnel oxide layer by electron tunneling across an entire portion of a tunneling channel upon incurrence of a sufficient voltage potential between a floating gate and the tunnel channel

Abstract translation: 描述了通过P阱中的隧道通道的电子隧道编程和擦除的两个晶体管EEPROM单元。 EEPROM单元具有形成在半导体衬底中的两个晶体管。 两个晶体管是隧道晶体管（NMOS）和读取晶体管（NMOS）。 发生电子隧穿，以在浮动栅极和隧道通道之间发生足够的电压电势时通过隧道氧化物层通过电子隧穿跨越隧道通道的整个部分来编程和擦除EEPROM单元

公开(公告)号：US5854114A

公开(公告)日：1998-12-29

申请号：US947888

申请日：1997-10-09

Applicant: Xiao-Yu Li ,  Radu Barsan ,  Sunil D. Mehta

Inventor： Xiao-Yu Li ,  Radu Barsan ,  Sunil D. Mehta

IPC: H01L21/762 ,  H01L21/8239 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L21/336

CPC classification number: H01L27/11517 ,  H01L21/76229 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11526

Abstract: A shallow trench isolation structure and a method for forming the same for use with non-volatile memory devices is provided so as to maintain sufficient data retention thereof. An epitaxial layer is formed on a top surface of a semiconductor substrate. A barrier oxide layer is formed on a top surface of the epitaxial layer. A nitride layer is deposited on a top surface of the barrier oxide layer. Trenches are formed through the epitaxial layer and the barrier oxide layer to a depth greater than 4000 .ANG. below the surface of the epitaxial layer so as to create isolation regions in order to electrically isolate active regions in the epitaxial layer. A liner oxide is formed on sidewalls and bottom of the trenches to a thickness between 750 .ANG. to 1500 .ANG.. As a result, leakage current in the sidewalls are prevented due to less thinning of the liner oxide layer by subsequent fabrication process steps.

公开(公告)号：US5841701A

公开(公告)日：1998-11-24

申请号：US785096

申请日：1997-01-21

Applicant: Xiao-Yu Li ,  Radu Barsan ,  Sunil Mehta

Inventor： Xiao-Yu Li ,  Radu Barsan ,  Sunil Mehta

IPC: G11C16/10 ,  G11C16/12 ,  G11C11/34

CPC classification number: G11C16/12 ,  G11C16/10

Abstract: A method for improving the endurance and reliability of a floating gate transistor often used in memory applications by controlling the electric field induced across the tunnel oxide region of the floating gate when discharging electrons from the floating gate. The method comprises the steps of: allowing the active region to ground; and applying a program voltage to the floating gate over a period of time and at a magnitude, by increasing the voltage from zero volts to the magnitude over a first period of at least 1 millisecond (ms.), maintaining the voltage at the magnitude for a second period of around 10 ms.-100 ms. sufficient to place charge on the floating gate, and decreasing the voltage from the magnitude during a third period to zero volts in not greater than 50 microseconds.

Abstract translation: 常用于存储器应用中的浮栅晶体管的耐久性和可靠性通过控制在浮置栅极放电电子时跨越浮栅的隧道氧化物区域感应的电场的方法。 该方法包括以下步骤：允许有源区域接地; 并且通过在至少1毫秒（ms）的第一周期上将电压从零伏特增加到幅度，在一段时间和幅度上将编程电压施加到浮动栅极，将电压保持在大小为 大约10 ms.-100 ms的第二个周期。 足以在浮动栅极上放置电荷，并将电压从第三周期内的幅度降低到零伏特以不大于50微秒。

公开(公告)号：US08748557B2

公开(公告)日：2014-06-10

申请号：US13220386

申请日：2011-08-29

Applicant: Xiao-Yu Li ,  Jun Ye ,  Hai-Qiao Wang ,  Teng Qiu

Inventor： Xiao-Yu Li ,  Jun Ye ,  Hai-Qiao Wang ,  Teng Qiu

IPC: C08G12/12 ,  C08G12/34

CPC classification number: C08G12/36 ,  C08L61/24

Abstract: The present invention relates to an extreme low formaldehyde emission UF resin with a novel structure, and a process for its preparation. This UF resin is produced from formaldehyde, urea, a long chain multi-aldehyde prepolymer, and some modifiers. Its process follows three steps: weak caustic, weak acid and weak caustic. By using this prepolymer, the modified UF resin has stable alkyl ether structure, and the residual aldehyde groups on the UF polymer chain could accelerate cross-linking instead of dissociative formaldehyde. The UF resin made from this invention has extreme low dissociative formaldehyde and simple technology. The boards produced from this resin have good physical performance and water resistance. Moreover, the formaldehyde emission of the boards is extreme low, achieving Japan F⋆⋆⋆⋆ grade, the average emission value ≦0.3 mg/L.

Abstract translation: 本发明涉及具有新颖结构的极低甲醛释放的UF树脂及其制备方法。 该UF树脂由甲醛，尿素，长链多醛预聚物和一些改性剂制备。 其过程分为三个步骤：弱碱，弱酸和弱碱。 通过使用该预聚物，改性UF树脂具有稳定的烷基醚结构，UF聚合物链上残留的醛基可加速交联而不是解离甲醛。 由本发明制成的UF树脂具有极低的解离甲醛和简单的技术。 由该树脂生产的板具有良好的物理性能和耐水性。 此外，板的甲醛释放量极低，达到日本F⋆⋆⋆⋆等级，平均排放值nlE; 0.3 mg / L。

公开(公告)号：US08732039B1

公开(公告)日：2014-05-20

申请号：US12981382

申请日：2010-12-29

Applicant: Maomao Chen ,  Xiao Yu Li

Inventor： Maomao Chen ,  Xiao Yu Li

IPC: G06Q10/00

CPC classification number: G06Q10/087 ,  G06Q10/063 ,  G06Q30/0202

Abstract: Methods and systems for allocating regional inventory to reduce out-of-stock costs are described. A method may include identifying a total number of units of an item to be stored in a plurality of regions and determining an order forecast for the item in each of the plurality of regions. The method may also include receiving a unit out-of-stock cost of the item in each of the plurality of regions and calculating an expected cost for each of the plurality of regions based, at least in part, on the total number of units of the item, each region's respective order forecast, and each region's respective unit out-of-stock cost. The method may further include allocating a portion of the total number of units of the item to each of the plurality of regions to reduce a sum of the expected costs.

Abstract translation: 描述了分配区域库存以减少库存成本的方法和系统。 方法可以包括识别要存储在多个区域中的项目的单元的总数，并且确定多个区域中的每个区域中的项目的顺序预测。 该方法还可以包括：在多个区域中的每个区域中接收项目的单位缺货成本，并且至少部分地基于多个区域中的每个区域的总单位数来计算多个区域中的每个区域的预期成本 该项目，每个区域各自的订单预测，以及每个区域各自的单位缺货成本。 该方法还可以包括将该项目的单元的总数的一部分分配给多个区域中的每个区域以减少预期成本的总和。

公开(公告)号：US08620707B1

公开(公告)日：2013-12-31

申请号：US13172153

申请日：2011-06-29

Applicant: Dmitriy Belyi ,  Xiao Yu Li

Inventor： Dmitriy Belyi ,  Xiao Yu Li

IPC: G06Q10/00

CPC classification number: G06Q10/087

Abstract: Systems and methods systems and methods for allocating inventory in a fulfillment network are disclosed. In some embodiments, a method may include identifying orders fulfilled by a fulfillment center, where each of the identified orders specifies one or more of a plurality of items. The method may also include determining, for each identified order, a probability that the identified order will occur in the future and calculating, for each identified order, a cost savings. Items may then be selected based, at least in part, upon the determined probability and cost savings of each identified order. Additionally or alternatively, a method may include, for a selected item, receiving a customer demand forecast, determining a bind factor, and calculating a target inventory for the selected item to be stored in the fulfillment center based, at least in part, upon the customer demand forecast and the bind factor.

Abstract translation: 公开了用于在履行网络中分配库存的系统和方法系统和方法。 在一些实施例中，方法可以包括识别由履行中心实现的订单，其中每个所识别的订单指定多个项目中的一个或多个。 该方法还可以包括为每个确定的顺序确定所识别的顺序将来将发生的概率，并且为每个确定的订单计算成本节约。 然后可以至少部分地基于确定的每个确定的订单的概率和成本节省来选择项目。 另外或替代地，方法可以包括，对于所选择的项目，至少部分地基于所选择的项目，接收客户需求预测，确定绑定因子，以及计算要存储在履行中心中的所选项目的目标库存 客户需求预测和绑定因素。

公开(公告)号：US08612596B1

公开(公告)日：2013-12-17

申请号：US12751032

申请日：2010-03-31

Applicant: Xiao Yu Li ,  Diwakar Gupta ,  Akshay Kumar Reddy Katta ,  Sergey Krasnovsky ,  Kalyanaraman Prasad

Inventor： Xiao Yu Li ,  Diwakar Gupta ,  Akshay Kumar Reddy Katta ,  Sergey Krasnovsky ,  Kalyanaraman Prasad

IPC: G06F15/173

CPC classification number: G06Q30/0202 ,  G06F9/50 ,  G06F2209/5019

Abstract: Disclosed are various embodiments for the planning of resources used in computing. Usage statistics regarding one or more machine instances executing in a plurality of networked computing devices are obtained. The usage statistics are grouped based at least in part on one or more customer usage classifications, thereby producing one or more usage groups. A corresponding demand forecast is generated for each of the usage groups. A projected demand for one or more physical components of the networked computing devices is calculated according to the demand forecasts.

Abstract translation: 公开了用于计算中使用的资源的规划的各种实施例。 获得关于在多个网络计算设备中执行的一个或多个机器实例的使用统计。 使用统计信息至少部分地基于一个或多个客户使用分类来分组，从而产生一个或多个使用组。 为每个使用组生成相应的需求预测。 根据需求预测计算出对网络计算设备的一个或多个物理组件的预计需求。

公开(公告)号：US06291327B1

公开(公告)日：2001-09-18

申请号：US09192094

申请日：1998-11-13

Applicant: Xiao-Yu Li ,  Sunil D. Mehta ,  Christopher O. Schmidt ,  Robert H. Tu

Inventor： Xiao-Yu Li ,  Sunil D. Mehta ,  Christopher O. Schmidt ,  Robert H. Tu

IPC: H01L21336

CPC classification number: H01L21/76237 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/1052

Abstract: A method for eliminating source/drain shorting generated during the highly-doped source/drain implant steps in a standard STI process is provided. This is achieved by reducing the RTA temperature to be less than 1000° C. so as to minimize enhanced doping diffusion. Further, the energy level for the highly-doped source/drain implant steps is increased so to compensate for poly depletion in the gate electrodes.

Abstract translation: 提供了一种用于消除在标准STI工艺中的高掺杂源极/漏极注入步骤期间产生的源极/漏极短路的方法。 这是通过将RTA温度降低至小于1000℃来实现的，以便使增强的掺杂扩散最小化。 此外，高掺杂源极/漏极注入步骤的能级增加，以补偿栅电极中的多晶硅耗尽。

公开(公告)号：US06274898B1

公开(公告)日：2001-08-14

申请号：US09316241

申请日：1999-05-21

Applicant: Sunil D. Mehta ,  Xiao-Yu Li

Inventor： Sunil D. Mehta ,  Xiao-Yu Li

IPC: H01L27108

CPC classification number: H01L27/11521 ,  G11C16/0441 ,  H01L27/115 ,  H01L27/11558

Abstract: A triple-well EEPROM cell is described that is programmed and erased by electron tunneling across an entire portion of separate transistor channels. The EEPROM cell has three transistors formed in a semiconductor substrate. The three transistors are a tunneling transistor (NMOS), a sense transistor (NMOS) and a read transistor (NMOS). The tunneling transistor is formed in a second well (e.g a P conductivity type well) that is separated from the substrate by a first well, having e.g. an N conductivity type. a first well formed in the substrate. Electron tunneling occurs to program the EEPROM cell through a sense tunnel oxide layer upon incurrence of a sufficient voltage potential between a floating gate and the sense channel. Electron tunneling also occurs to erase the EEPROM cell through a tunnel oxide layer upon incurrence of a sufficient voltage potential between the floating gate and the tunneling channel.

Abstract translation: 描述了通过遍及分离的晶体管通道的整个部分的电子隧道编程和擦除的三阱EEPROM单元。 EEPROM单元具有形成在半导体衬底中的三个晶体管。 三个晶体管是隧道晶体管（NMOS），感测晶体管（NMOS）和读取晶体管（NMOS）。 隧道晶体管形成在第二阱（例如P导电型阱）中，第二阱由第一阱与衬底分离，第一阱具有例如第二阱。 N导电型。 在衬底中形成的第一阱。 发生电子隧穿，以在浮动栅极和感测通道之间发生足够的电压电势时通过感测隧道氧化物层来编程EEPROM单元。 当浮置栅极和隧穿通道之间产生足够的电压电势时，也会发生电子隧穿，以通过隧道氧化物层擦除EEPROM单元。

公开(公告)号：US06255169B1

公开(公告)日：2001-07-03

申请号：US09255053

申请日：1999-02-22

Applicant: Xiao-Yu Li ,  Qi Xiang ,  Sunil D. Mehta

Inventor： Xiao-Yu Li ,  Qi Xiang ,  Sunil D. Mehta

IPC: H01L218247

CPC classification number: H01L27/11521 ,  H01L27/11558

Abstract: A process for fabricating a non-volatile memory device includes the step of forming a nitrogen region in a semiconductor substrate prior to carrying out a thermal oxidation process to form a tunnel oxide layer. In a preferred process, nitrogen atoms are ion implanted into a silicon substrate to form a nitrogen region at the substrate surface. Then, a thermal oxidation process is carried out to grow a thin tunnel oxide layer overlying the surface of the nitrogen region. During the oxidation process, nitrogen is incorporated into the growing tunnel oxide layer. A floating-gate electrode is formed overlying the tunnel oxide layer and receives electrical charge transferred from a charge control region of the substrate through the tunnel oxide layer. The tunnel oxide layer is capable of undergoing repeated programming and erasing operations while exhibiting reduced effects from stress induced current leakage. In another aspect of the invention, an MOS transistor having enhanced carrier mobility is obtained by forming a gate oxide layer over a nitrogen region of a silicon substrate. The thermal oxidation process of the invention also provides both tunnel oxide layers and gate oxide layers having a reduced thickness for a given set of thermal oxidation conditions.

Abstract translation: 一种用于制造非易失性存储器件的方法包括在进行热氧化工艺以形成隧道氧化物层之前在半导体衬底中形成氮区的步骤。 在优选的方法中，将氮原子离子注入到硅衬底中以在衬底表面形成氮区。 然后，进行热氧化处理，以生长覆盖在氮区域的表面上的薄的隧道氧化物层。 在氧化过程中，将氮气掺入生长的隧道氧化物层中。 在隧道氧化物层上形成浮栅电极，并接收通过隧道氧化物层从衬底的电荷控制区转移的电荷。 隧道氧化物层能够经受重复的编程和擦除操作，同时表现出应力感应电流泄漏的减小的影响。 在本发明的另一方面，通过在硅衬底的氮区上形成栅极氧化层，获得具有增强的载流子迁移率的MOS晶体管。 本发明的热氧化方法还为给定的一组热氧化条件提供具有减小的厚度的隧道氧化物层和栅极氧化物层。