公开(公告)号：US5767930A

公开(公告)日：1998-06-16

申请号：US859338

申请日：1997-05-20

Applicant: Kazuhiro Kobayashi ,  Yuichi Masutani ,  Hiroyuki Murai

Inventor： Kazuhiro Kobayashi ,  Yuichi Masutani ,  Hiroyuki Murai

IPC: H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  G02F1/136 ,  H01L29/04 ,  H01L31/036 ,  H01L29/76

CPC classification number: H01L27/1214 ,  H01L29/78621 ,  H01L29/78627

Abstract: An active-matrix liquid crystal display integrally formed with a driver circuit including: a pair of substrates disposed in opposing relation to each other; and a liquid crystal material sandwiched between the pair of substrates, wherein the pair of substrates includes: a TFT substrate including at least an insulative substrate, source interconnection line and gate interconnection line which are formed in a matrix pattern on the insulative substrate, a thin film transistor provided to each pixel portion for use as a switching element for applying a voltage to a portion of the liquid crystal material which lies at a location where the source interconnection line and the gate interconnection line intersect each other, a pixel electrode connected to a drain electrode of the thin film transistor for supplying a voltage to the liquid crystal material, and a CMOS driver circuit having a CMOS which comprises thin film transistors for supplying an electric signal to the thin film transistor of the pixel portion through the source interconnection line and the gate interconnection line; and a counterpart substrate including an insulative substrate and a counter electrode formed thereon, the thin film transistor provided to the pixel portion being of a first conductivity type and of an offset or LDD structure, at least a first conductivity type thin film transistor of the thin film transistors of the CMOS driver circuit being of an offset or LDD structure.

Abstract translation: 一种与驱动电路一体形成的有源矩阵液晶显示器，包括：一对基板，彼此相对设置; 以及夹在所述一对基板之间的液晶材料，其中，所述一对基板包括：至少在所述绝缘基板上形成为矩阵图案的绝缘基板，源极配线和栅极互连配线的TFT基板，薄型 提供给每个像素部分的薄膜晶体管用作用于向位于源极互连线和栅极互连线彼此相交的位置处的液晶材料的一部分施加电压的开关元件，连接到 用于向液晶材料提供电压的薄膜晶体管的漏极电极以及具有CMOS的CMOS驱动电路，CMOS电路包括用于通过源极互连线向像素部分的薄膜晶体管提供电信号的薄膜晶体管，以及 门互连线; 以及包括形成在其上的绝缘基板和对置电极的对置基板，所述薄膜晶体管设置在所述像素部分上，所述像素部分具有第一导电类型和偏移或LDD结构，所述薄膜晶体管至少具有薄的第一导电型薄膜晶体管 CMOS驱动电路的薄膜晶体管具有偏移或LDD结构。

公开(公告)号：US09645457B2

公开(公告)日：2017-05-09

申请号：US11943976

申请日：2007-11-21

Applicant: Yuichi Masutani ,  Shigeaki Noumi ,  Takeshi Shimamura ,  Masaru Aoki

Inventor： Yuichi Masutani ,  Shigeaki Noumi ,  Takeshi Shimamura ,  Masaru Aoki

IPC: B44C1/17 ,  G03C5/00 ,  G02F1/1362

CPC classification number: G02F1/1362 ,  G02F2201/48 ,  Y10T428/24802

Abstract: An array substrate has regions in which an intermediate resist film thickness is formed and processed by an intermediate exposure amount which does not completely expose a resist, respectively on a drain electrode, source terminal, and a common connection wiring which are made of a second conductive film. Thin film patterns or a common wiring made of a first conductive film is formed in substantially entire regions on the bottom layers of the regions so that the heights from a substrate are substantially the same.

公开(公告)号：US07982838B2

公开(公告)日：2011-07-19

申请号：US11396458

申请日：2006-04-04

Applicant: Shingo Nagano ,  Yuichi Masutani

Inventor： Shingo Nagano ,  Yuichi Masutani

IPC: G02F1/1343 ,  G02F1/1333

CPC classification number: G02F1/134363 ,  G02F2001/136218

Abstract: Source lines cross, over an intervening first insulation film, gate lines on an insulation substrate. Switching elements are on crossings between the gate lines and the source lines. Pixel electrodes are connected to the switching elements. Common electrodes facing the pixel electrodes generate between the pixel electrodes and the common electrodes an electric field directed approximately parallel to the insulation substrate. First shielding electrode patterns along the source lines in a layer, with the first insulation film intervening, underneath the source lines, at least partially overlap the source lines widthwise. Plural second shielding electrode patterns are formed along the source lines, overlapping the first shielding electrode patterns and without substantially overlapping the source lines in a layer, with a second insulation film intervening, above the source lines. The first shielding electrode patterns having a same electric potential as the plural second shielding electrode patterns.

Abstract translation: 源极线穿过中间的第一绝缘膜，绝缘基板上的栅极线。 开关元件位于栅极线和源极线之间的交叉点上。 像素电极连接到开关元件。 面对像素电极的公共电极在像素电极和公共电极之间产生大致平行于绝缘衬底的电场。 沿着源极线下方的第一绝缘膜在源极线之间沿着源极线的第一屏蔽电极图案至少部分地与源极线宽度重叠。 沿着源极线形成多个第二屏蔽电极图案，与第一屏蔽电极图案重叠，并且在源极线之上没有与第二绝缘膜基本上重叠在一个层中的源极线。 第一屏蔽电极图案具有与多个第二屏蔽电极图案相同的电位。

公开(公告)号：US20090243641A1

公开(公告)日：2009-10-01

申请号：US12411990

申请日：2009-03-26

Applicant: Shigeaki NOUMI ,  Yuichi MASUTANI

Inventor： Shigeaki NOUMI ,  Yuichi MASUTANI

IPC: G01R31/02

CPC classification number: G02F1/13452 ,  G09G3/006 ,  G09G3/3611 ,  G09G2300/0426

Abstract: An array substrate is provided with thereon a display area in which plural pixels are arranged in a matrix shape. Output-side mounting terminals for a source driving circuit chip, which is COG-mounted on a frame area on the outside of the display area, have a plural-row zigzag arrangement. Inspection terminals individually provided in correspondence to the output-side mounting terminals have a zigzag arrangement opposite to the zigzag arrangement of the output-side mounting terminals in a terminal-row direction. Additionally, the output-side mounting terminals and the inspection terminals are disposed below the source driving circuit chip.

Abstract translation: 在阵列基板上设置有以矩阵形状排列有多个像素的显示区域。 用于COG安装在显示区域外侧的框架区域上的源极驱动电路芯片的输出侧安装端子具有多行Z字形布置。 与输出侧安装端子对应地分别设置的检查端子具有与端子排方向上的输出侧安装端子的Z字形排列相对的Z字形排列。 此外，输出侧安装端子和检查端子设置在源极驱动电路芯片的下方。

公开(公告)号：US07554634B2

公开(公告)日：2009-06-30

申请号：US11548488

申请日：2006-10-11

Applicant: Yuichi Masutani ,  Shigeaki Noumi ,  Shingo Nagano

Inventor： Yuichi Masutani ,  Shigeaki Noumi ,  Shingo Nagano

IPC: G02F1/1335 ,  G02F1/1343

CPC classification number: G02F1/133555 ,  G02F1/136227

Abstract: A thin film transistor array substrate includes a reflective electrode, a storage capacitor electrode disposed below the reflective electrode with a first insulation layer interposed therebetween, a second insulation layer disposed above the reflective electrode, the second insulation layer having a contact hole in an area where the storage capacitor electrode is not disposed, a transmissive electrode electrically connected to the reflective electrode through the contact hole, and a thickness compensation pattern disposed below the reflective electrode in an area having the contact hole. The thickness compensation pattern is isolated from the storage capacitor electrode.

Abstract translation: 薄膜晶体管阵列基板包括反射电极，设置在反射电极下方的辅助电容电极，其间插入有第一绝缘层，设置在反射电极上方的第二绝缘层，第二绝缘层在其中 不设置保持电容电极，通过接触孔与反射电极电连接的透射电极和设置在具有接触孔的区域中的反射电极下方的厚度补偿图案。 厚度补偿图案与存储电容器电极隔离。

公开(公告)号：US07535522B2

公开(公告)日：2009-05-19

申请号：US11151533

申请日：2005-06-14

Applicant: Kenichi Watanabe ,  Yuichi Masutani ,  Shigeaki Noumi ,  Hitoshi Morishita ,  Hiroshi Ueda

Inventor： Kenichi Watanabe ,  Yuichi Masutani ,  Shigeaki Noumi ,  Hitoshi Morishita ,  Hiroshi Ueda

IPC: G02F1/1333 ,  G02F1/1345

CPC classification number: G02F1/13452 ,  G02F1/1309

Abstract: A liquid crystal display of the present invention comprises a display portion having two opposed insulating substrates (an electrode substrate (1) and an opposed substrate 2) holding a liquid crystal layer to form a plurality of display elements, wires (3a) formed on at least one of the insulating substrates, for supplying signals to the plurality of display elements, a driver LSI (6) provided in a peripheral portion of the insulating substrate, being connected to terminals of the wires (3a, 3b) to drive a plurality of display elements, and a conductive film pattern portion formed on the wires (3a) in the peripheral portion of the insulating substrate with a first insulating layer interposed therebetween. With this constitution, a liquid crystal display which allows inspection of output signals of the driver LSI in a failure analysis, without extending wires or exposing electrode portions connected to the wires and a method of inspecting the liquid crystal display are provided.

Abstract translation: 本发明的液晶显示器包括具有两个相对的绝缘基板（电极基板（1）和相对的基板2）的显示部分，该基板保持液晶层以形成多个显示元件， 用于向多个显示元件提供信号的至少一个绝缘基板，设置在绝缘基板的周边部分的驱动器LSI（6），与导线（3a，3b）的端子连接以驱动多个 显示元件和形成在绝缘基板的周边部分中的导线（3a）上的导电膜图案部分，其间插入有第一绝缘层。 利用这种结构，提供了一种液晶显示器，其能够在故障分析中检查驱动器LSI的输出信号，而不延伸连接到电线的电线或暴露电极部分以及检查液晶显示器的方法。

公开(公告)号：US07315340B2

公开(公告)日：2008-01-01

申请号：US11276136

申请日：2006-02-15

Applicant: Yuichi Masutani ,  Shingo Nagano

Inventor： Yuichi Masutani ,  Shingo Nagano

IPC: G02F1/1335

CPC classification number: G02F1/133553 ,  G02F1/136213 ,  G02F2203/09

Abstract: The present invention provides a transflective liquid crystal display device that has reflective contrast reduction preventing electrodes formed in given positions and that is capable of preventing bright dot defects while preventing reduction of reflective contrast. In a reflective region in a pixel region, a reflective electrode is formed in the same layer as source bus lines and separated by given spaces from the source bus lines. Reflective contrast reduction preventing electrodes are formed above the given spaces and have areas overlapping the reflective electrode in plane view, with an insulating film formed between them. The reflective contrast reduction preventing electrodes are in an electrically floating state.

Abstract translation: 本发明提供一种半透射型液晶显示装置，其具有形成在给定位置的反射减少防止电极，并且能够防止亮点缺陷同时防止反射对比度的降低。 在像素区域的反射区域中，反射电极形成在与源极总线相同的层中，并且与源极总线分开给定的空间。 在给定空间上方形成反射对比度降低防止电极，并且在平面图中具有与反射电极重叠的区域，并且在它们之间形成绝缘膜。 反射对比度降低防止电极处于电浮动状态。

公开(公告)号：US20060289869A1

公开(公告)日：2006-12-28

申请号：US11372086

申请日：2006-03-10

Applicant: Shinji Yamashita ,  Yuichi Masutani ,  Shingo Nagano

Inventor： Shinji Yamashita ,  Yuichi Masutani ,  Shingo Nagano

IPC: H01L29/04

CPC classification number: G02F1/133555 ,  G02F1/136213 ,  G02F1/136259

Abstract: A contrast reduction preventive electrode is formed in a reflective region, and in the same layer as a transparent pixel electrode. A connection for connecting the contrast reduction preventive electrode and the transparent pixel electrode is formed, in such a position that the connection does not overlap an auxiliary capacitive wiring in plan view. When a short circuit is generated between the surfaces of the contrast reduction preventive electrode and an opposed electrode (not shown), the contrast reduction preventive electrode is cut off from the transparent pixel electrode at the connection.

Abstract translation: 防反射电极形成在反射区域中，与透明像素电极在同一层中形成。 形成用于连接对比度降低预防电极和透明像素电极的连接，使得连接在平面图中不与辅助电容布线重叠。 当在对比电极（未示出）的表面之间产生短路时，在连接时从透明像素电极切断对比度降低预防电极。

公开(公告)号：US20060262056A1

公开(公告)日：2006-11-23

申请号：US11279482

申请日：2006-04-12

Applicant: Yuichi MASUTANI ,  Naoki Nakagawa ,  Shinji Kawabuchi ,  Shigeru Yachi ,  Kazunori Okumoto ,  Yukio Ijima ,  Takayuki Fukuda

Inventor： Yuichi MASUTANI ,  Naoki Nakagawa ,  Shinji Kawabuchi ,  Shigeru Yachi ,  Kazunori Okumoto ,  Yukio Ijima ,  Takayuki Fukuda

IPC: G09G3/36

CPC classification number: G06F3/0412 ,  G09G3/3611

Abstract: The present invention provides a display device capable of reducing cost by reduction in number of integrators. Signal lines (91 to 94, 95 to 98, 99 to 912, 913 to 916) are brought together into one line by means of signal lines (10a, 10b, 10c, 10d) to be connected to integrators (4a, 4b, 4c, 4d), respectively. Selector lines (71 to 74) orthogonal to the signal lines (91 to 916) are formed and connected to a selector driving circuit (3). An a-SiTFT (12) is formed at each of intersections: an intersection of the selector line (71) and the signal lines (91, 95, 99, 913); an intersection of the selector line (72) and the signal lines (92, 96, 910, 914); an intersection of the selector line (73) and the signal lines (93, 97, 911, 915); and an intersection of the selector line (74) and the signal lines (94, 98, 912, 916). The selector lines (71 to 74) are driven in sequence by the selector driving circuit (3) in the frame period.

Abstract translation: 本发明提供一种能够通过减少积分器的数量来降低成本的显示装置。 信号线（9 1至9 4，9 5至9 8，9 9， 通过信号线（10a，10b）连接到一条线路中，并且通过信号线（10a，10b，...，13,13 ，10c，10d）分别连接到积分器（4a，4b，4c，4d）。 与信号线（9 1〜9 16）正交的选择线（7 <1> 1〜7> 4）是 形成并连接到选择器驱动电路（3）。 在每个交点处形成a-SiTFT（12）：选择器线（7I 1）和信号线（9＆lt; 1＆gt;，9＆ 5，9 9，9 13）; 选择器线（7）2和信号线（9＆lt; 2＆gt;，9＆lt; 6＆gt;，＆lt; 10＆lt; >，9＆lt; 14＆gt;）; 选择器线（7 3 3）与信号线（9，3，9，9，11）之间的交叉点 >，9 <15>）; 以及选择器线（7S4X）与信号线（9）的交叉点（9＆lt; 4＆gt;，9＆lt; 8＆gt; 9＆lt; 16＆gt;）。 选择器线（7 1〜7 4）在帧期间由选择器驱动电路（3）依次驱动。

公开(公告)号：US5838037A

公开(公告)日：1998-11-17

申请号：US858693

申请日：1997-05-19

Applicant: Yuichi Masutani ,  Yoshinori Numano ,  Kazuhiro Kobayashi

Inventor： Yuichi Masutani ,  Yoshinori Numano ,  Kazuhiro Kobayashi

IPC: G02F1/1343 ,  G02F1/136 ,  G02F1/1368 ,  G09F9/35 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L27/108 ,  H01L27/01

CPC classification number: H01L27/1214 ,  G02F1/134363

Abstract: A TFT-array including a substrate, a gate electrode, a first and second electrode provided on the substrate simultaneously with the gate electrode, an insulating film formed on the gate electrode, the first and the second electrode, a semiconductor layer formed on the gate electrode in such a manner that the insulating film is interposed between the semiconductor layer and the gate electrode, a pair of electrodes, either of which is connected with the first electrode or the second electrode, said pair of electrodes defining a semiconductor element together with the semiconductor layer.

Abstract translation: 一种TFT阵列，包括基板，栅电极，与栅电极同时设置在基板上的第一和第二电极，形成在栅电极上的绝缘膜，第一和第二电极，形成在栅极上的半导体层 电极，其中所述绝缘膜插入在所述半导体层和所述栅电极之间，一对电极，其中的任一个与所述第一电极或所述第二电极连接，所述一对电极与所述半导体元件一起限定 半导体层。