摘要:
Disclosed herein are a structure of a metal oxide semiconductor pseudomorphic high electron mobility transistor (MOS-PHEMT) suitable for use in a semiconductor device, such as a single-pole-double-throw (SPDT) switch of a monolithic microwave integrated circuit (MMIC); and a method of producing the same. The MOS-PHEMT structure is characterized in having a gate dielectric layer formed by atomic deposition from a gate dielectric selected from the group consisting of Al2O3, HfO2, La2O3, and ZrO2, and thereby rendering the semiconductor structure comprising the same, such as a high frequency switch device, to have less DC power loss, less insertion loss and better isolation.
摘要翻译:本文公开了适用于单片微波集成电路(MMIC)的单极双掷(SPDT)开关的半导体器件中的金属氧化物半导体假晶高电子迁移率晶体管(MOS-PHEMT)的结构 ); 及其制造方法。 MOS-PHEMT结构的特征在于具有通过从由Al 2 O 3,HfO 2,La 2 O 3和ZrO 2组成的组中选择的栅极电介质的原子沉积形成的栅极电介质层,从而使包含其的半导体结构如高 频率开关器件,具有较小的直流功率损耗,更少的插入损耗和更好的隔离。
摘要:
Panchromatic photosensitizers having a Formula of ML1L2X were synthesized, wherein M comprises ruthenium atom; X is a monodentate anion; L1 is heterocyclic bidentate ligand having one of formulae listed below: wherein G2 has one of formulae listed below: and L2 is a tridentate ligand having a formula listed below: The substituents R1, R2, R3, R4, R5, R6, R7 of L1 and L2 are the same or different, and represent alkyl, alkoxy, alkylthio, alkylamino, halogenated alkyl, phenyl or substituted phenyl group, carboxylic acid or counter anion thereof, sulfonic acid or counter anion thereof, phosphoric acid or counter anion thereof, amino-group, halogens, or hydrogen. The above-mentioned photosensitizers are suitable to use as sensitizers for fabrication of high efficiency dye-sensitized solar cell.
摘要:
Systems and methods for classifying documents each having zero or more links thereto include generating a link matrix; generating a document term matrix; and jointly factorizing the document term matrix and the link matrix.
摘要:
There is disclosed herein phosphorescent compounds, uses thereof, and devices including organic light emitting diode (OLEDs) including such compounds.Compounds of interest include: wherein A is Os or Ru The anionic chelating chromophores N^N, which are formed by connecting one pentagonal ring structure containing at least two nitrogen atoms to a hexagonal pyridine type of fragment via a direct carbon-carbon linkage.L is a neutral donor ligand; the typical example includes carbonyl, pyridine, phosphine, arsine and isocyanide; two neutral L's can also combine to produce the so-called chelating ligand such as 2,2′-bipyridine, 1,10-phenanthroline and N-heterocyclic carbene (NHC) ligand, or bidentate phosphorous ligands such as 1,2-bis(diphenylphosphino)ethane, 1,2-bis(diphenylphosphino)benzene.L can occupy either cis or trans orientation.When L occupies the trans position, the preferred structure contains both the hexagonal fragment of N^N as well as its pentagonal fragment located at the trans position respect to their counterparts of the second N^N chromophore.When L occupies the cis position, the preferred structure consists of the pentagonal unit of N^N chromophores residing opposite to the L. X,1 X2 and X3 independently are C or N; when X2 is N, R1 is omitted, when X3 is N, R2 is omitted, R1 is H, C1-C8 alkyl, C1-C8 substituted phenyl or C1-C4 perfluoroalkyl, R2 is H, F or cyano substituent, X4 is either C or N; X4 may locate at any position of the hexagonal ring, when X4 is N and R3 and R4 are not linked to X4, R3 is H, methyl or C1-C3 small alkyl, R4 is H, methyl or C1-C3 small alkyl, or R3 and R4 together form an additional conjugated unit with structure
摘要:
This invention provides a method for forming polysilicon by using silane with introducing hydrogen, such that polysilicon is microcrystalline. This microcrystal polysilicon can be applied to floating gate of flash memory to improve the character of flash memory.
摘要:
An apparatus and method are provided for suppressing the input current inrush for a voltage converter in a pre-charge stage. The voltage converter comprises a power input for receiving an input current, a power output for supplying an output voltage for a load, and an output capacitor connected to the power output. In a pre-charge stage, a current limiting device is connected between the power input and the output capacitor to limit the input current to flow therethrough, and a variable current limiting control circuit provides a control signal to the current limiting device to determine a variable maximum value for the input current.
摘要:
Load shedding schemes for mining data streams. A scoring function is used to rank the importance of stream elements, and those elements with high importance are investigated. In the context of not knowing the exact feature values of a data stream, the use of a Markov model is proposed herein for predicting the feature distribution of a data stream. Based on the predicted feature distribution, one can make classification decisions to maximize the expected benefits. In addition, there is proposed herein the employment of a quality of decision (QoD) metric to measure the level of uncertainty in decisions and to guide load shedding. A load shedding scheme such as presented herein assigns available resources to multiple data streams to maximize the quality of classification decisions. Furthermore, such a load shedding scheme is able to learn and adapt to changing data characteristics in the data streams.
摘要:
Systems and methods for classifying documents each having zero or more links thereto include generating a link matrix; generating a document term matrix; and jointly factorizing the document term matrix and the link matrix.
摘要:
The present invention discloses a level shift circuit which comprises: a basic level shift circuit for receiving inputs of first high and low operational voltage levels and generating outputs of second low and high operational voltage levels at a first node; and an output circuit for outputting a signal of one of the second operational voltage levels according to a voltage level switching at the first node.
摘要:
A yield enhancement system has a fabrication line with semiconductor fabrication devices for fabricating a wafer, an inspection and measurement monitoring system coupled to the fabrication line for determining process data corresponding to semiconductor fabrication devices, and a post-process testing line coupled to the fabrication line for performing in-line wafer-level testing. The post-process testing line includes a wafer acceptance tester, a yield monitor coupled to the wafer acceptance tester, and a wafer level reliability tester coupled to the wafer acceptance tester for estimating a life span of a device on the wafer.